Abstract: In a nonvolatile semiconductor memory device according to the present invention, a password protection function is enabled or disabled based on a first specified value M and a second state specified value P such that when both of the first specified value M and the second state specified value P are in a set state, the password protection function is enabled and when at least the second specified value P is in a reset state, the password protection function is disabled, and the first state specified value M maintains a previous state and the second state specified value P follows the state of the first state specified value M in response to a reset operation, and the cancel operation to shift the second state specified value P to the reset state can be performed only when the password is inputted correctly.

Abstract: In a nonvolatile semiconductor memory device according to the present invention, a password protection function is enabled or disabled based on a first specified value M and a second state specified value P such that when both of the first specified value M and the second state specified value P are in a set state, the password protection function is enabled and when at least the second specified value P is in a reset state, the password protection function is disabled, and the first state specified value M maintains a previous state and the second state specified value P follows the state of the first state specified value M in response to a reset operation, and the cancel operation to shift the second state specified value P to the reset state can be performed only when the password is inputted correctly.

Abstract: A semiconductor storage device includes: a memory cell array including a plurality of memory cells which are connected to a plurality of pairs of complementary bit lines; an internal voltage decreasing section for generating a predetermined voltage lower than a power supply voltage; and an equalizing section for performing an equalizing operation to charge the pairs of complementary bit lines to a predetermined equal potential, wherein the internal voltage decreasing section is formed by first and second internal voltage decreasing sections, the equalizing section is formed by a first equalizing section, which is provided at one side of the memory cell array, and a second equalizing section, which is provided at the other side of the memory cell array, the first and second internal voltage decreasing sections supply an electric power to the first and second equalizing sections, respectively.

Abstract: A charging circuit includes a charging driving circuit, a time constant circuit, a control circuit, a voltage detection circuit, and a delay and inversion circuit. The charging driving circuit starts a charging operation in accordance with a delay signal output from the delay and inversion circuit, and terminates the charging operation in accordance with a detection signal output from the voltage detection circuit.

Abstract: A charging circuit includes a charging driving circuit, a time constant circuit, a control circuit, a voltage detection circuit, and a delay and inversion circuit. The charging driving circuit starts a charging operation in accordance with a delay signal output from the delay and inversion circuit, and terminates the charging operation in accordance with a detection signal output from the voltage detection circuit.

Abstract: A charging circuit includes a charging driving circuit, a time constant circuit, a control circuit, a voltage detection circuit, and a delay and inversion circuit. The charging driving circuit starts a charging operation in accordance with a delay signal output from the delay and inversion circuit, and terminates the charging operation in accordance with a detection signal output from the voltage detection circuit.

Abstract: A semiconductor storage device includes: a memory cell array including a plurality of memory cells which are connected to a plurality of pairs of complementary bit lines; an internal voltage decreasing section for generating a predetermined voltage lower than a power supply voltage; and an equalizing section for performing an equalizing operation to charge the pairs of complementary bit lines to a predetermined equal potential, wherein the internal voltage decreasing section is formed by first and second internal voltage decreasing sections, the equalizing section is formed by a first equalizing section, which is provided at one side of the memory cell array, and a second equalizing section, which is provided at the other side of the memory cell array, the first and second internal voltage decreasing sections supply an electric power to the first and second equalizing sections, respectively.

Abstract: A charging circuit includes a charging driving circuit, a time constant circuit, a control circuit, a voltage detection circuit, and a delay and inversion circuit. The charging driving circuit starts a charging operation in accordance with a delay signal output from the delay and inversion circuit, and terminates the charging operation in accordance with a detection signal output from the voltage detection circuit.