Abstract: In a test circuit, a determination circuit conducts a function test to determine whether timing of a slope section of waveform of an analog signal ANS of a measurement target device is within a range of specifications. An ADC performs AD-conversion only when a potential of analog signal ANS is within a range between reference potentials VOL, VOH. An analysis unit analyzes digital data from the ADC, and conducts a sloping waveform test to evaluate a sloping state of the waveform of analog signal ANS. Therefore, the slope section of the waveform of analog signal ANS of the device can be subjected to AD-conversion in a voltage range divided in arbitrary number of sections within a range of arbitrary voltage amplitude without requiring a large-capacity storage circuit. The function test by a determination circuit and the sloping waveform test by the analysis unit can be performed in parallel.

Abstract: An apparatus for testing a semiconductor integrated circuit has a test circuit board and an ancillary test device. The ancillary test device can test a digital circuit. The ancillary test device has test pattern memory, a test pattern signal generator, and a control section for controlling an operation for the test pattern data selected from among the plurality of test pattern data sets stored in the test pattern memory and an operation for writing the selected test pattern data into the test pattern signal generator. The ancillary test device generates a test input pattern signal on the basis of test pattern data written in the test pattern signal generator and determines a test output pattern signal output from the semiconductor integrated circuit on the basis of the test input pattern signal, thereby testing a digital circuit.

Abstract: A data storage apparatus comprising a scrambling circuit 34 for converting address signals and error data output by a tester 24 to a desired format, and a storage device 28 for storing the converted data. The scrambling circuit 34 includes a plurality of conversion circuits 40, 42 and 44 each converting the signals from the tester 24 according to different rules, and a selector 46 for selecting one of signals output by the conversion circuits 40, 42 and 44 and for supplying what is selected to the storage device.

Abstract: The interface circuit includes n buffer circuits, switches for connecting an external pin of a tester to input nodes of n buffer circuits and connecting output nodes of n buffers respectively to n DUTs when a signal is provided from the tester to n DUTs, and successively connecting n DUTs to the external pin of the tester by a prescribed time period when voltage-ampere characteristics of n DUTs are measured. Therefore the number of devices that can be measured by the tester at a time can be increased by n times. As a result, the test cost can be reduced and the test accuracy can be improved.

Abstract: A jitter measurement circuit includes: a conversion section sampling one of a reference signal and a measurement target signal in response to the other of the signals, thereby obtaining a sampling data string; and a determination section measuring jitter of the measurement target signal on the basis of the sampling data string obtained by the conversion section. Since the reference signal is a stable signal having a predetermined cycle, the sampling data string as a measurement result depends on the measurement target signal. Therefore, it is possible to simply measure jitter level in accordance with irregularity of the measurement result and on the basis of relative measurement to expected value data.

Abstract: In a test circuit, a determination circuit conducts a function test to determine whether timing of a slope section of waveform of an analog signal ANS of a measurement target device is within a range of specifications. An ADC performs AD-conversion only when a potential of analog signal ANS is within a range between reference potentials VOL, VOH. An analysis unit analyzes digital data from the ADC, and conducts a sloping waveform test to evaluate a sloping state of the waveform of analog signal ANS. Therefore, the slope section of the waveform of analog signal ANS of the device can be subjected to AD-conversion in a voltage range divided in arbitrary number of sections within a range of arbitrary voltage amplitude without requiring a large-capacity storage circuit. The function test by a determination circuit and the sloping waveform test by the analysis unit can be performed in parallel.

Abstract: A test ancillary device with data memory and an analysis section is disposed in the vicinity of a test circuit board. The data memory is divided into two memory sections such that, when digital test data are stored in one memory section, the digital test data that have already been stored in the other memory section are loaded for analysis purpose.

Abstract: An apparatus for testing a semiconductor integrated circuit has a test circuit board and an ancillary test device. The ancillary test device can test a digital circuit. The ancillary test device has test pattern memory, a test pattern signal generator, and a control section for controlling an operation for the test pattern data selected from among the plurality of test pattern data sets stored in the test pattern memory and an operation for writing the selected test pattern data into the test pattern signal generator. The ancillary test device generates a test input pattern signal on the basis of test pattern data written in the test pattern signal generator and determines a test output pattern signal output from the semiconductor integrated circuit on the basis of the test input pattern signal, thereby testing a digital circuit.

Abstract: The interface circuit includes n buffer circuits, switches for connecting an external pin of a tester to input nodes of n buffer circuits and connecting output nodes of n buffers respectively to n DUTs when a signal is provided from the tester to n DUTs, and successively connecting n DUTs to the external pin of the tester by a prescribed time period when voltage-ampere characteristics of n DUTs are measured. Therefore the number of devices that can be measured by the tester at a time can be increased by n times. As a result, the test cost can be reduced and the test accuracy can be improved.

Abstract: There is provided an apparatus and method of testing a semiconductor integrated circuit, which apparatus and method enable testing of various semiconductor integrated circuits having different characteristics, fulfillment of the function of generating DAC data, and adaptation of various analog characteristic tests. An input range of a BOST device is switchable in accordance with the level of a DAC of a DUT, so that the test apparatus can handle DUTs of different types having different analog output levels.

Abstract: A jitter measurement circuit includes: a conversion section sampling one of a reference signal and a measurement target signal in response to the other signal, thereby obtaining a sampling data string; and a determination section measuring jitter of the measurement target signal on the basis of the sampling data string obtained by the conversion section. Since the reference signal is a stable signal having a predetermined cycle, the sampling data string as a measurement result depends on the measurement target signal. Therefore, it is possible to simply measure jitter level in accordance with irregularity of the measurement result and on the basis of relative measurement to expected value data.

Abstract: There are provided a test apparatus and method for testing a semiconductor integrated circuit which enables improvements in the ease of operation and convenience of a BOST device and shortening of a test time. Numeric codes are assigned to tests. A test apparatus is equipped with memory and an analysis section. A test requirement table—in which hardware requirements required for conducting a test are set on a per-numeric-code basis—is stored in the memory. Test requirements corresponding to a numeric code are read from the memory, whereupon a test is performed. The analysis section analyzes a digital test output and sends the result of analysis to an external controller.

Abstract: A test-assisting device (BOST device) is provided in the vicinity of a testing circuit board that transmits signals to and receive signals from a semiconductor integrated circuit to be tested, and the D/A converter circuit for testing, the A/D converter circuit for testing, the measured-data memory, and the analyzing portion of the test-assisting device are carried by separate circuit boards.

Abstract: A BOST (built-off self-test) board has a connector, a substrate for use with a BOST board, and an external self-test circuit. The external self-test circuit has an ADC (analog-to-digital converter)/DAC (digital-to-analog converter) measurement section and a DSP (digital signal processor). In accordance with a control signal input by way of a specific terminal provided in a connector, the ADC/DAC measurement section transmits a predetermined test signal to the specific terminal provided in the connector. Further, in response to the test signal, the ADC/DAC measurement section receives a response signal input to the specific terminal provided in the connector. The DSP analysis section analyzes the response signal, thereby determining whether or not the response signal is an appropriate signal. Further, the DSP analysis section transmits, to the specific terminal provided in the connector, a test result signal indicating whether or not the response signal is appropriate.

Abstract: A semiconductor test apparatus includes an analog-to-digital converter for converting into a digital signal an analog output from a circuit under test; a test-apparatus-ADC-control-signal generation circuit for generating a control signal for the analog-to-digital converter in accordance with an activation signal entered from the outside; a measured data memory for storing, as measured data for each conversion, a signal output from the analog-to-digital converter; an address counter for generating an address signal for the measured data memory; a DAC counter for generating data to be input to the circuit under test; and a data write control circuit which produces, in response to a flag signal output from the analog-to-digital converter and representing that conversion is being performed, an update signal for the address counter, a memory write signal for the measured data memory, and an update signal for the DAC counter.

Abstract: To provide a tester for semiconductor integrated circuits that can test an A/D converter circuit and a D/A converter circuit in a mixed signal type semiconductor integrated circuit comprising an A/D converter circuit and a D/A converter circuit at high accuracy and at high speed. A test assisting device is provided in the vicinity of a testing circuit board on which a semiconductor integrated circuit to be tested is mounted. The test assisting device comprises a data circuit to supply analog test signals to the A/D converter circuit of the semiconductor integrated circuit to be tested, and digital test signals to the D/A converter circuit thereof, a measured data memory to store test outputs from the semiconductor integrated circuit to be tested, and an analyzer portion to analyze data stored in the measured data memory.

Abstract: In a threshold analysis method obtaining threshold voltages of all bits in a flash memory through single processing, fail bit map information is examined in order from a smaller voltage applied to the flash memory. As to a bit exhibiting a value, read from the flash memory, first mismatching a determination value, the threshold voltage is settled on the basis of a voltage applied when the bit fails in reading.

Abstract: There are provided a test apparatus and a test method for testing a semiconductor integrated circuit which facilitate control of a BOST device and improve the versatility of the BOST device. There is provided an interface for exchanging signals between a BOST device and an external controller. A test control signal and a test result analysis signal are exchanged by means of the interface, thus effecting a test and analysis of the test.

Abstract: A semiconductor test apparatus and method for performing a test on a nonvolatile semiconductor memory such as a flash memory while preventing excessive erasing with reliability. In each erase operation, all addresses are scanned to fetch an error address and error data into a catch memory. Then, on the basis of error information (error address and error data), a rewrite operation is performed to write data on all memory cells. The write data varies according to a comparison result between an address signal and an error address signal. If they disagree, a “0” is written on a memory cell at the address. If they agree, a “0” is written on a “pass” memory cell and a “1” is virtually written on a fail memory cell.

Abstract: Semiconductor test apparatus and method are provided to perform a test on a nonvolatile semiconductor memory such as a flash memory while preventing excessive erasing with reliability. In each erase operation (step S62), all addresses are scanned to fetch an error address and error data into a catch memory (step S253). Then, on the basis of error information (error address and error data), a rewrite operation is performed to write data on all memory cells. Write data varies according to a comparison result between an address signal (118) and an error address signal (181) (steps S257-267). If they disagree, a “0” is written on a memory cell at the address (step S261). If they agree, a “0” is written on a “pass” memory cell and a “1” is virtually written on a “fail” memory cell (step S260).