Patents by Inventor Teruhiko Kamigata
Teruhiko Kamigata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10747699Abstract: A bus control circuit configured to transfer access commands for performing exclusive access between a first bus specification and a second bus specification by converting from a first exclusive access command applying to the first bus specification which deals with exclusive access, into a second exclusive access command of the second bus specification which doesn't deal with the exclusive access.Type: GrantFiled: February 12, 2019Date of Patent: August 18, 2020Assignee: SOCIONEXT INCInventors: Takayuki Otani, Teruhiko Kamigata, Takashi Kawasaki, Eiichi Nimoda
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Publication number: 20190188173Abstract: A bus control circuit for transferring an exclusive command between first and second bus specifications by mutually converting a first exclusive command of the first bus specification which deals with an exclusive access, and a second exclusive command of the second bus specification which doesn't deal with the exclusive access, includes an exclusive command conversion circuit receiving the first exclusive command, converting and outputting the second exclusive command, when converting from the first to second exclusive commands; an exclusive command generation circuit receiving the second exclusive command and generating the first exclusive command, when converting from the second to first exclusive commands; an exclusive response issuing circuit issuing exclusive response information for the second exclusive command, when converting from the second to first exclusive commands; and an exclusive response receiving circuit receiving exclusive response information for the second exclusive command, when convertiType: ApplicationFiled: February 12, 2019Publication date: June 20, 2019Inventors: Takayuki OTANI, Teruhiko KAMIGATA, Takashi KAWASAKI, Eiichi NIMODA
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Patent number: 8839210Abstract: To provide a program performance analysis apparatus that can present to a user whether tuning made to a program operating on a predetermined hardware is either good or bad, a performance information acquisition unit for obtaining the performance information of a program, a difference information generation unit for generating difference information by making a comparison between the performance information of a first program and that of a second program obtained by making a change to the first program, and a change evaluation unit for evaluating whether the change is either good or bad are comprised.Type: GrantFiled: March 23, 2009Date of Patent: September 16, 2014Assignee: Fujitsu LimitedInventors: Teruhiko Kamigata, Atsuhiro Suga, Shigeru Kimura
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Patent number: 8732441Abstract: A multiprocessing system includes a storage part that stores to a memory, a first operating system (OS) task set that is constituted by a combination of a first task and a first OS corresponding to the first task, the first task being designated by an execution instruction; and a task executing part that refers to the first OS task set stored to the memory, loads the OS constituting the first OS task set, and executes the first task designated by the execution instruction.Type: GrantFiled: September 14, 2009Date of Patent: May 20, 2014Assignee: Fujitsu LimitedInventor: Teruhiko Kamigata
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Patent number: 7647473Abstract: An instruction processing method for checking an arrangement of basic instructions in a very long instruction word (VLIW) instruction, suitable for language processing systems, an assembler and a compiler, used for processors which execute variable length VLIW instructions designed based on variable length VLIW architecture.Type: GrantFiled: January 24, 2002Date of Patent: January 12, 2010Assignee: Fujitsu LimitedInventors: Teruhiko Kamigata, Hideo Miyake
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Publication number: 20100005275Abstract: A multiprocessing system includes a storage part that stores to a memory, a first operating system (OS) task set that is constituted by a combination of a first task and a first OS corresponding to the first task, the first task being designated by an execution instruction; and a task executing part that refers to the first OS task set stored to the memory, loads the OS constituting the first OS task set, and executes the first task designated by the execution instruction.Type: ApplicationFiled: September 14, 2009Publication date: January 7, 2010Applicant: FUJITSU LIMITEDInventor: Teruhiko Kamigata
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Publication number: 20090217247Abstract: To provide a program performance analysis apparatus that can present to a user whether tuning made to a program operating on a predetermined hardware is either good or bad, a performance information acquisition unit for obtaining the performance information of a program, a difference information generation unit for generating difference information by making a comparison between the performance information of a first program and that of a second program obtained by making a change to the first program, and a change evaluation unit for evaluating whether the change is either good or bad are comprised.Type: ApplicationFiled: March 23, 2009Publication date: August 27, 2009Applicant: FUJITSU LIMITEDInventors: Teruhiko Kamigata, Atsuhiro Suga, Shigeru Kimura
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Patent number: 7409506Abstract: A multiprocessor system includes a plurality of processors, a shared bus coupled to the plurality of processors, a resource coupled to the shared bus and shared by the plurality of processors, and an exclusive control unit coupled to the plurality of processors and configured to include a lock flag indicative of a locked/unlocked state regarding exclusive use of the resource, wherein the processors include a special purpose register interface coupled to the exclusive control unit, and are configured to access the lock flag by special purpose register access through the special purpose register interface.Type: GrantFiled: April 25, 2005Date of Patent: August 5, 2008Assignee: Fujitsu LimitedInventors: Teruhiko Kamigata, Shinichiro Tago, Atsushi Ike, Yoshimasa Takebe
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Patent number: 7134004Abstract: An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.Type: GrantFiled: September 20, 2000Date of Patent: November 7, 2006Assignee: Fujitsu LimitedInventors: Shin-ichiro Tago, Taizo Sato, Yoshimasa Takebe, Yasuhiro Yamazaki, Teruhiko Kamigata, Atsuhiro Suga, Hiroshi Okano, Hitoshi Yoda
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Publication number: 20060224870Abstract: The present invention is defined in that an information processing device which reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing comprises: an instruction reading request portion which assigns a read address to the instruction store portion; an instruction buffering portion including a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion; a branching instruction detection portion which detects a branching instruction in the instruction sequence read from the instruction store portion; and a branch target address information buffering portion including a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target addreType: ApplicationFiled: May 31, 2006Publication date: October 5, 2006Inventors: Shin-ichiro Tago, Taizo Sato, Yoshimasa Takebe, Yasuhiro Yamazaki, Teruhiko Kamigata, Atsuhiro Suga, Hiroshi Okano, Hitoshi Yoda
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Patent number: 7117315Abstract: Data shared by plural processes of a program are identified and identification information is affixed to the shared data. When the program is linked by a linker, only the shared data to which identification information is affixed are extracted and a shared data area is created for the shared data. During program execution, this shared data area is prevented from being and the main memory is referred to or updated or the cache is invalidated prior to access of the shared data area by the linker. An address of data in a processor is computed from an address of the data in another processor based on a specific expression.Type: GrantFiled: June 25, 2003Date of Patent: October 3, 2006Assignee: Fujitsu LimitedInventors: Hideo Miyake, Teruhiko Kamigata, Akiko Azegami
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Publication number: 20060143416Abstract: A multiprocessor system includes a plurality of processors, a shared bus coupled to the plurality of processors, a resource coupled to the shared bus and shared by the plurality of processors, and an exclusive control unit coupled to the plurality of processors and configured to include a lock flag indicative of a locked/unlocked state regarding exclusive use of the resource, wherein the processors include a special purpose register interface coupled to the exclusive control unit, and are configured to access the lock flag by special purpose register access through the special purpose register interface.Type: ApplicationFiled: April 25, 2005Publication date: June 29, 2006Inventors: Teruhiko Kamigata, Shinichiro Tago, Atsushi Ike, Yoshimasa Takebe
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Publication number: 20050289334Abstract: In a computer system having a plurality of processing elements (PE#0 to PE#n) and adopting a distributed-shared-memory-type multiprocessor scheme, a master PE (for example, PE#0) executing a multi PE loader transfers an MPMD program for PE#k to a predetermined area of memory space of PE#0 to which a unique memory (LM) of PE#k is temporally allocated. The LMs of PE#1 to PE#n can be allocated to different areas of the memory space of PE#0 respectively, or can be allocated the same area thereof.Type: ApplicationFiled: May 24, 2005Publication date: December 29, 2005Inventors: Tomohiro Yamana, Teruhiko Kamigata, Hideo Miyake, Atsuhiro Suga
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Patent number: 6868472Abstract: In a cache memory control method and computer of the present invention, a cache memory is connected to a main memory and divided into a plurality of cache blocks, and a lock/unlock signal is supplied to the cache memory to either set a replace-inhibition state of at least one of the cache blocks in which replacing at least one of the cache blocks to the main memory is inhibited, or reset the replace-inhibition state of at least one of the cache clocks such that replacing at least one of the cache block to the main memory is allowed. Either reading or writing of the main memory is performed by using the remaining cache blocks of the cache memory, other than the at least one of the cache blocks, such that, when the replace-inhibition state is set by the lock/unlock signal, replacing the at least one of the cache blocks to the main memory is inhibited during the reading or writing of the main memory.Type: GrantFiled: September 28, 2000Date of Patent: March 15, 2005Assignee: Fujitsu LimitedInventors: Hideo Miyake, Atsuhiro Suga, Yasuki Nakamura, Teruhiko Kamigata, Hitoshi Yoda, Hiroshi Okano, Yoshio Hirose
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Publication number: 20040055000Abstract: Data shared by plural processes of a program are identified and identification information is affixed to the shared data. When the program is linked by a linker, only the shared data to which identification information is affixed are extracted and a shared data area is created. During program execution, this shared data area is uncached and always the main memory is referred or updated. Or, cache is invalidated prior to access of the shared data by the linker. An address of a data of a processor is computed from an address of the data in another processor based on a specific expression.Type: ApplicationFiled: June 25, 2003Publication date: March 18, 2004Applicant: FUJITSU LIMITEDInventors: Hideo Miyake, Teruhiko Kamigata, Akiko Azegami
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Publication number: 20020161986Abstract: An instruction processing method for checking an arrangement of basic instructions in a very long instruction word (VLIW) instruction, suitable for language processing systems, an assembler and a compiler, used for processors which execute variable length VLIW instructions designed based on variable length VLIW architecture.Type: ApplicationFiled: January 24, 2002Publication date: October 31, 2002Applicant: FUJITSU LIMITEDInventors: Teruhiko Kamigata, Hideo Miyake