Abstract: The objective of the invention is to read and write data in synchronization with a high-speed clock signal. The pulse width of the timing control signal (FY signal), which determines the pulse width of the column select signal (YS signal), is enlarged in a data read operation and reduced in a data write operation. In this way, the activation pulse width of the column select signal is enlarged in a data read operation and reduced in a data write operation. Consequently, in a data read operation, the time for connecting a bit line pair to an input/output line pair becomes longer. The potential difference of the bit line pair can be completely transferred to the input/output line pair. Therefore, data can be read correctly in synchronization with a high-speed clock signal.