Abstract: A reset signal generation circuit for generating a reset signal synchronously or asynchronously to a clock signal in accordance with an operation state. An operation detection circuit detects operation of a CPU and generates an operation detection signal. A signal control circuit generates a first reset signal synchronously or asynchronously to an internal clock signal based on the operation detection signal and a system reset signal. The first reset signal is provided to synchronous circuits including the CPU.

Abstract: A semiconductor integrated circuit device has a pair of oscillator terminals that is respectively provided with two oscillation signals having phases opposite to each other. An oscillator circuit provides an internal circuit with a system clock signal based on the oscillation signals. A mode detection circuit detects that the pair of oscillator terminals is respectively provided with two input signals having the same phase, and provides a test circuit with a detection signal. The test circuit sets a test mode according to the detection signal, and provides the internal circuit with a predetermined test signal. By setting the test mode using a pair of external terminals, an increase in the number of external terminals of the semiconductor integrated circuit device can be prevented.

Abstract: A reset signal generation circuit for generating a reset signal synchronously or asynchronously to a clock signal in accordance with an operation state. An operation detection circuit detects operation of a CPU and generates an operation detection signal. A signal control circuit generates a first reset signal synchronously or asynchronously to an internal clock signal based on the operation detection signal and a system reset signal. The first reset signal is provided to synchronous circuits including the CPU.

Abstract: A reset signal generation circuit for generating a reset signal synchronously or asynchronously to a clock signal in accordance with an operation state. An operation detection circuit detects operation of a CPU and generates an operation detection signal. A signal control circuit generates a first reset signal synchronously or asynchronously to an internal clock signal based on the operation detection signal and a system reset signal. The first reset signal is provided to synchronous circuits including the CPU.

Abstract: To present a reset control circuit and a reset control method used in a system including clock synchronous circuit, capable of resetting appropriately, especially in case of abnormality, when the clock signal is stopped or its period is longer as compared with the reset response required for detection of abnormal state. A reset control circuit 200 for output control of reset signal RS depending on reset request signal RR comprises a clock transforming unit 210 for transforming and issuing a clock signal CK, while generating a clock output signal RC at delay of clock output waiting period DC depending on the reset request signal RR, and a reset signal generator 220 for generating a reset signal RS at delay of reset output waiting period D depending on the clock output signal RC.

Abstract: A reset signal generation circuit for generating a reset signal synchronously or asynchronously to a clock signal in accordance with an operation state. An operation detection circuit detects operation of a CPU and generates an operation detection signal. A signal control circuit generates a first reset signal synchronously or asynchronously to an internal clock signal based on the operation detection signal and a system reset signal. The first reset signal is provided to synchronous circuits including the CPU.

Abstract: A system for efficiently developing an LSI. A developing system includes a developing apparatus and a support center, which are connected to each other via the Internet. The host computer of the developing apparatus designs the software of a system LSI in accordance with a user's instruction. An emulator debugger sends design data to the support center. The support center performs a predetermined process on the received design data and notifies the processing result to a host computer via the Internet.

Abstract: A semiconductor integrated circuit device has a pair of oscillator terminals that is respectively provided with two oscillation signals having phases opposite to each other. An oscillator circuit provides an internal circuit with a system clock signal based on the oscillation signals. A mode detection circuit detects that the pair of oscillator terminals is respectively provided with two input signals having the same phase, and provides a test circuit with a detection signal. The test circuit sets a test mode according to the detection signal, and provides the internal circuit with a predetermined test signal. By setting the test mode using a pair of external terminals, an increase in the number of external terminals of the semiconductor integrated circuit device can be prevented.

Abstract: A spread spectrum clock generation circuit capable of further reducing the electromagnetic wave radiation with a simple configuration has been disclosed and, particularly in a spread spectrum clock generation circuit using a current control oscillator (ICO), a differential signal to which a spread spectrum modulation signal, the period or amplitude of which changes, is added is generated, and the differential signal is applied to the ICO and a clock is generated.

Abstract: A semiconductor integrated circuit device has a pair of oscillator terminals that is respectively provided with two oscillation signals having phases opposite to each other. An oscillator circuit provides an internal circuit with a system clock signal based on the oscillation signals. A mode detection circuit detects that the pair of oscillator terminals is respectively provided with two input signals having the same phase, and provides a test circuit with a detection signal. The test circuit sets a test mode according to the detection signal, and provides the internal circuit with a predetermined test signal. By setting the test mode using a pair of external terminals, an increase in the number of external terminals of the semiconductor integrated circuit device can be prevented.

Abstract: To present a reset control circuit and a reset control method used in a system including clock synchronous circuit, capable of resetting appropriately, especially in case of abnormality, when the clock signal is stopped or its period is longer as compared with the reset response required for detection of abnormal state. A reset control circuit 200 for output control of reset signal RS depending on reset request signal RR comprises a clock transforming unit 210 for transforming and issuing a clock signal CK, while generating a clock output signal RC at delay of clock output waiting period DC depending on the reset request signal RR, and a reset signal generator 220 for generating a reset signal RS at delay of reset output waiting period D depending on the clock output signal RC.

Abstract: A spread spectrum clock generation circuit capable of further reducing the electromagnetic wave radiation with a simple configuration has been disclosed and, particularly in a spread spectrum clock generation circuit using a current control oscillator (ICO), a differential signal to which a spread spectrum modulation signal, the period or amplitude of which changes, is added is generated, and the differential signal is applied to the ICO and a clock is generated.

Abstract: A spread spectrum clock generation circuit capable of further reducing the electromagnetic wave radiation with a simple configuration has been disclosed and, particularly in a spread spectrum clock generation circuit using a current control oscillator (ICO), a differential signal to which a spread spectrum modulation signal, the period or amplitude of which changes, is added is generated, and the differential signal is applied to the ICO and a clock is generated.

Abstract: A semiconductor integrated circuit device has a pair of oscillator terminals that is respectively provided with two oscillation signals having phases opposite to each other. An oscillator circuit provides an internal circuit with a system clock signal based on the oscillation signals. A mode detection circuit detects that the pair of oscillator terminals is respectively provided with two input signals having the same phase, and provides a test circuit with a detection signal. The test circuit sets a test mode according to the detection signal, and provides the internal circuit with a predetermined test signal. By setting the test mode using a pair of external terminals, an increase in the number of external terminals of the semiconductor integrated circuit device can be prevented.

Abstract: A spread spectrum clock generation circuit capable of further reducing the electromagnetic wave radiation with a simple configuration has been disclosed and, particularly in a spread spectrum clock generation circuit using a current control oscillator (ICO), a differential signal to which a spread spectrum modulation signal, the period or amplitude of which changes, is added is generated, and the differential signal is applied to the ICO and a clock is generated.

Abstract: A system for efficiently developing an LSI. A developing system includes a developing apparatus and a support center, which are connected to each other via the Internet. The host computer of the developing apparatus designs the software of a system LSI in accordance with a user's instruction. An emulator debugger sends design data to the support center. The support center performs a predetermined process on the received design data and notifies the processing result to a host computer via the Internet.