Abstract: A multilayer coil component 1 includes an element body, a first terminal electrode, a second terminal electrode, a coil, a first connecting conductor, and a second connecting conductor, the coil includes first wiring portions, second wiring portions, and pillar portions, and lengths of the pillar portions in a first direction are longer than lengths of the pillar portions in a third direction.

Abstract: Provided is a multilayer coil component including an element body, a first terminal electrode, a second terminal electrode, a coil, a first connecting conductor, and a second connecting conductor, wherein a length of each of the first connecting conductor and the second connecting conductor in a first direction is longer than lengths of pillar portions connected to the first connecting conductor and the second connecting conductor in the first direction and equal to or less than lengths of the first terminal electrode and the second terminal electrode in the first direction.

Abstract: Provided is a multilayer coil component in which a position of a boundary between a first portion and a third portion in a second wiring portion located closer to a side surface is located closer to an end surface in a first direction than a position of a boundary between a first portion and a third portion in a second wiring portion located closer to a side surface, and a position of a boundary between a second portion and a third portion in a second wiring portion located closer to the side surface is located closer to an end surface in the first direction than a position of a boundary between a second portion and a third portion in a second wiring portion located closer to the side surface.

Abstract: A laminated coil component includes an element body, a first terminal electrode and a second terminal electrode, and a coil, the coil includes a first wiring portion, a second wiring portion, and a pillar portion, the pillar portion has a first pillar member and a second pillar member alternately laminated in a second direction, and an area of a first surface and an area of a second surface of the first pillar member are larger than an area of a first surface and an area of a second surface of the second pillar member, or smaller than the area of the first surface and the area of the second surface of the second pillar member.

Abstract: A laminated coil component includes an element body, a first terminal electrode and a second terminal electrode, and a coil, the coil includes a plurality of first wiring portions disposed on a main surface side and disposed side by side in a third direction, a plurality of second wiring portions disposed on a mounting surface side and disposed side by side in the third direction, and a plurality of first pillar portions and second pillar portions that extend in a second direction and connect the first wiring portion with the second wiring portion which correspond to each other, and a width of the second wiring portion in the third direction is smaller than a width of the first wiring portion in the third direction.

Abstract: A multilayer coil component includes an element body including a main surface (a mounting surface) and a main surface, a pair of terminal electrodes disposed on the main surface of the element body, and a coil that is disposed in the element body and electrically connected to the pair of terminal electrodes, wherein the element body includes at least one element body layer containing a filler and at least one element body layer having a lower dielectric constant than the element body layer between a first wiring portion and the terminal electrodes.

Abstract: For marking a package efficiently at low cost, there is provided a dicing sheet 25 having transfer patterns 28A, 28B and an alignment mark 31 disposed at predetermined positions on a main surface of a base material 26, and an orientation flat 32 of a semiconductor wafer 1 and the alignment mark 31 are aligned with each other, then the main surface of the dicing sheet with the transfer patterns 28A, 28B and the alignment mark 31 disposed thereon and a back surface of the semiconductor wafer 1 are affixed to each other, and thereafter heat and pressure are applied to a back surface of the dicing sheet 25, thereby allowing the transfer patterns 28A and 28B to be transferred at a time to back surfaces of semiconductor chips from the dicing sheet 25.

Abstract: The package size of a diode is made smaller. On the element forming face of a semiconductor substrate having a p−-type conductive type, after a hyper-abrupt p+n+ junction of a p+-type diffusion layer, an n+-type hyper-abrupt layer, an n−-epitaxial layer, an n-type low resistance layer and an n+-type diffusion layer is formed, an anode electrode is formed on the top of the p+-type diffusion layer and a cathode electrode is formed on the top of the n+-type diffusion layer. Thereafter, electrode bumps are formed on the top of the anode electrode and the cathode electrode to thereby manufacture a small diode that can be facedown bonded onto a mounting board.

Abstract: The package size of a diode is made smaller. On the element forming face of a semiconductor substrate having a p−-type conductive type, after a hyper-abrupt p+n+ junction of a p+-type diffusion layer, an n+-type hyper-abrupt layer, an n−-epitaxial layer, an n-type low resistance layer and an n+-type diffusion layer is formed, an anode electrode is formed on the top of the p+-type diffusion layer and a cathode electrode is formed on the top of the n+-type diffusion layer. Thereafter, electrode bumps are formed on the top of the anode electrode and the cathode electrode to thereby manufacture a small diode that can be facedown bonded onto a mounting board.