Abstract: A processor or a semiconductor integrated circuit has circuit blocks performing signal processing, internal power supply nets, noise detecting circuits corresponding to each circuit block that detect noise on the power supply nets and an interruption handling circuit that prevents a malfunction in processing within a circuit block caused by noise on the power supply nets. When noise is detected, the interruption handling circuit performs an interruption by sending an interruption signal to the circuit block relating to the signal processing for preventing a malfunction to the circuit block. During the operation of a plurality of stages for executing an instruction, noise is monitored at every stage. If no noise is detected through a final stage, the result is outputted. If noise is detected at any one of the stages, then an interruption process is performed.

Abstract: A processor or a semiconductor integrated circuit which prevents a malfunction caused by noise on power supply nets. A noise detecting circuit which detects noise on power supply nets to a circuit block is arranged in each of a plurality of circuit blocks which performs signal processing, and which performs interruption for preventing a malfunction to the circuit block itself or other circuit blocks relating to this signal processing by a detection signal of each noise detecting circuit.

Abstract: An on-chip multiprocessor having a chip layout for efficient multiprocessor control, wherein multiple processors and shared portions such as shared caches are symmetric with respect to a desired linear axis and a multiprocessor controller is located in the area containing said linear axis. This makes the distances between the processors and the controller equal and shorter, and also decreases differences in the distance between the controller and shared portions, thereby permitting higher speed processing of signals among these.

Abstract: A processor or a semiconductor integrated circuit which prevents a malfunction caused by noise on power supply nets. A noise detecting circuit which detects noise on power supply nets to a circuit block is arranged in each of a plurality of circuit blocks which performs signal processing, and which performs interruption for preventing a malfunction to the circuit block itself or other circuit blocks relating to this signal processing by a detection signal of each noise detecting circuit.

Abstract: Gas-permeable hard contact lenses are produced by hot press-stretching a crosslined gas-permeable hard contact lens material and then machining the press-stretched material. The gas-permeable hard contact lenses are formed from a crosslinked gas permeable hard contact lens material which is hot press-stretched to have a compression ration of 5 to 50% and a compression-flexure fracture strength of 300 to 1,500 g. Efficiently produced gas-permeable hard contact lenses are produced which are free of optical strains, excellent in transparency, small internal stress and comfortable to wear with improved durability strength.

Abstract: The invention is intended to provide a magnetic recording medium suitable for longitudinal recording, which has low medium noise and high coercivity. A magnetic recording medium includes a substrate 1 and a magnetic layer 2 formed on the substrate 1. The magnetic layer 2 consists of a mixture of a magnetic alloy and a non-magnetic compound. The magnetic alloy is Co-based, Fe-based, or CoFe-based, and the non-magnetic compound is selected from a group consisting of oxides and nitrides. The volume percentage of the non-magnetic compound in the entire volume of the mixed magnetic alloy and non-magnetic compound is preferably not less than about 2% and not more than about 30%.

Abstract: A clock distributing logic for distributing a clock signal in a circuit and reducing clock skew which occurs during the distributing of the clock signal in the circuit and a method for designing the same. The clock distributing logic includes at least two stages of clock amplifying gates for distributing the clock signal to source and sink sides of the circuit. Each of the at least two stages are successively connected to each other. Further, each of the at least two stages except a last stage includes clock amplifying gates of a same size providing a same driving ability. The last stage of clock amplifying gates includes clock amplifying gates of different sizes providing different driving abilities. The size of each clock amplifying gate of the last stage of clock amplifying gates is set to make the delay in distributing the clock signal in the circuit coincide with a desired clock signal distributing cycle.

Abstract: The invention is intended to provide a magnetic recording medium suitable for longitudinal recording, which has low medium noise and high coercivity. A magnetic recording medium includes a substrate 1 and a magnetic layer 2 formed on the substrate 1. The magnetic layer 2 consists of a mixture of a magnetic alloy and a non-magnetic compound. The magnetic alloy is Co-based, Fe-based, or CoFe-based, and the non-magnetic compound is selected from a group consisting of oxides and nitrides. The volume percentage of the non-magnetic compound in the entire volume of the mixed magnetic alloy and non-magnetic compound is preferably not less than about 2% and not more than about 30%.

Abstract: A first and a second magnetic layer are deposited on a substrate. The first magnetic layer has high magneto-optical effect at short wavelengths, but low perpendicular anisotropy. The second magnetic layer has low magneto-optical effect at short wavelengths, but high perpendicular anisotropy. The magnetic exchange coupling between the two magnetic layers results in a recording medium which has strong perpendicular anisotropy and high magneto-optical effect, even at short wavelengths.

Abstract: A memory management unit is capable of judging that a specific bit has been partially rewritten by checking it against a dummy bit stored in a tag memory which is included in the memory management unit and thus correcting a parity bit. Accordingly, it is possible to accurately execute a parity check operation and it is also possible to improve the throughput of the memory management unit and hence promote lowering in the cost.