Patents by Inventor Teruhito Ohnishi
Teruhito Ohnishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100283084Abstract: The bipolar transistor includes a heterojunction intrinsic base layer epitaxially grown on a collector layer. The intrinsic base layer is disposed on the collector layer surrounded by an isolation layer, and an N-type impurity layer is formed in a surface portion of the collector layer. The impurity concentration of the N-type impurity layer is higher than the impurity concentration of the collector layer under the N-type impurity layer. Between the N-type impurity layer and the intrinsic base layer, an epitaxially grown layer is formed, where the epitaxially grown layer is lower in impurity concentration than the N-type impurity layer and the intrinsic base layer.Type: ApplicationFiled: March 24, 2010Publication date: November 11, 2010Inventors: Teruhito Ohnishi, Ken Idota, Atsushi Nakamura
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Patent number: 7808358Abstract: An inductor includes a flat substrate and a conductor in a spiral shape having a plurality of turns. The plane on which the conductor is formed is substantially in parallel with a principal surface of the substrate. The turns of the conductor are equally spaced from each other in a direction parallel to the plane on which the conductor is formed. An outer one of the turns of the conductor is wider and thinner than an inner one of the turns of the conductor. A level of at least one of a top and a bottom of the conductor differs from one turn to another in a cross section vertical to the plane on which the conductor is formed.Type: GrantFiled: April 23, 2009Date of Patent: October 5, 2010Assignee: Panasonic CorporationInventors: Atsushi Nakamura, Shinichiro Hayashi, Teruhito Ohnishi
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Patent number: 7719031Abstract: A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.Type: GrantFiled: July 6, 2004Date of Patent: May 18, 2010Assignee: Panasonic CorporationInventors: Tohru Saitoh, Takahiro Kawashima, Ken Idota, Yoshihiko Kanzawa, Teruhito Ohnishi
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Publication number: 20090273429Abstract: An inductor includes a flat substrate and a conductor in a spiral shape having a plurality of turns. The plane on which the conductor is formed is substantially in parallel with a principal surface of the substrate. The turns of the conductor are equally spaced from each other in a direction parallel to the plane on which the conductor is formed. An outer one of the turns of the conductor is wider and thinner than an inner one of the turns of the conductor. A level of at least one of a top and a bottom of the conductor differs from one turn to another in a cross section vertical to the plane on which the conductor is formed.Type: ApplicationFiled: April 23, 2009Publication date: November 5, 2009Inventors: Atsushi NAKAMURA, Shinichiro HAYASHI, Teruhito OHNISHI
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Patent number: 7465969Abstract: A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.Type: GrantFiled: June 12, 2006Date of Patent: December 16, 2008Assignee: Panasonic CorporationInventors: Teruhito Ohnishi, Koichiro Yuki, Tsuneichiro Sano, Tohru Saitoh, Ken Idota, Takahiro Kawashima, Shigeki Sawada
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Publication number: 20070085167Abstract: A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.Type: ApplicationFiled: July 6, 2004Publication date: April 19, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Tohru Saitoh, Takahiro Kawashima, Ken Idota, Yoshihiko Kanzawa, Teruhito Ohnishi
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Patent number: 7145168Abstract: On an Si substrate 1, a buffer layer 2, a SiGe layer 3, and an Si cap layer 4 are formed. A mask is formed on the substrate, and then the substrate is patterned. In this manner, a trench 7a is formed so as to reach the Si substrate 1 and have the side faces of the SiGe layer 3 exposed. Then, the surface of the trench 7a is subjected to heat treatment for one hour at 750° C. so that Ge contained in a surface portion of the SiGe layer 3 is evaporated. Thus, a Ge evaporated portion 8 having a lower Ge content than that of other part of the SiGe layer 3 is formed in part of the SiGe layer 3 exposed at part of the trench 7a. Thereafter, the walls of the trench 7a are oxidized.Type: GrantFiled: November 24, 2004Date of Patent: December 5, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihiro Hara, Akira Asai, Gaku Sugahara, Haruyuki Sorada, Teruhito Ohnishi
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Patent number: 7135721Abstract: The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.Type: GrantFiled: June 22, 2004Date of Patent: November 14, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Toyoda, Koichiro Yuki, Takeshi Takagi, Teruhito Ohnishi, Minoru Kubo
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Patent number: 7129168Abstract: A method of estimating substrate temperature according to this invention includes the steps of epitaxially growing a Si-containing layer (103) on a SiGe layer (102) formed on a substrate for temperature estimation (101) constituted of a Si substrate under a reaction control condition; finding a relationship between a rate of growth of the Si-containing layer and a substrate temperature of the substrate for temperature estimation; epitaxially growing a Si-containing layer on a substrate for device fabrication as a subject of substrate temperature estimation under a reaction control condition; and estimating a substrate temperature of the substrate for device fabrication based on the rate of growth of the latter Si-containing layer and the relationship between the rate of growth of the former Si-containing layer (103) and the substrate temperature of the substrate for temperature estimation.Type: GrantFiled: October 24, 2003Date of Patent: October 31, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Katsuya Nozawa, Tohru Saitoh, Teruhito Ohnishi
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Publication number: 20060226446Abstract: A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.Type: ApplicationFiled: June 12, 2006Publication date: October 12, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Teruhito Ohnishi, Koichiro Yuki, Tsuneichiro Sano, Tohru Saitoh, Ken Idota, Takahiro Kawashima, Shigeki Sawada
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Publication number: 20060225642Abstract: A method of forming semiconductor crystal of the present invention comprises the steps of heating a Si substrate to clean a surface of the Si substrate, epitaxially growing Si crystal on the Si substrate inside a crystal growth chamber at a growth temperature lower than a substrate temperature of the Si substrate in the cleaning step and higher than a growth temperature at which SiGe crystal is epitaxially grown later, and epitaxially growing the SiGe crystal on the Si crystal.Type: ApplicationFiled: March 31, 2003Publication date: October 12, 2006Inventors: Yoshihiko Kanzawa, Tohru Saitoh, Akira Asai, Teruhito Ohnishi
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Patent number: 7109095Abstract: Immediately after a Si/SiGe film containing a contaminant is formed over all surfaces of a substrate by epitaxial growth, a portion of the Si/SiGe film formed to the back surface side of the substrate is removed by wet etching. In addition, the Si/SiGe film is subjected to processing with heating in a container, after which a dummy run is carried out in the container. These processings prevent secondary wafer contamination through a stage, a robot arm or a vacuum wand for handling a wafer and the contamination of the container also used in the fabrication process of a semiconductor device free from any group IV element but Si.Type: GrantFiled: March 26, 2003Date of Patent: September 19, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hidenori Notake, Teruhito Ohnishi, Akira Asai, Shigetaka Aoki
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Patent number: 7091099Abstract: A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.Type: GrantFiled: March 24, 2004Date of Patent: August 15, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Teruhito Ohnishi, Koichiro Yuki, Tsuneichiro Sano, Tohru Saitoh, Ken Idota, Takahiro Kawashima, Shigeki Sawada
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Publication number: 20060126701Abstract: A method of estimating substrate temperature according to this invention includes the steps of epitaxially growing a Si-containing layer (103) on a SiGe layer (102) formed on a substrate for temperature estimation (101) constituted of a Si substrate under a reaction control condition; finding a relationship between a rate of growth of the Si-containing layer and a substrate temperature of the substrate for temperature estimation; epitaxially growing a Si-containing layer on a substrate for device fabrication as a subject of substrate temperature estimation under a reaction control condition; and estimating a substrate temperature of the substrate for device fabrication based on the rate of growth of the latter Si-containing layer and the relationship between the rate of growth of the former Si-containing layer (103) and the substrate temperature of the substrate for temperature estimation.Type: ApplicationFiled: October 24, 2003Publication date: June 15, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Katsuya Nozawa, Tohru Saitoh, Teruhito Ohnishi
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Patent number: 7049681Abstract: A Si1-xGex layer 111b functioning as the base composed of an i-Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111a as the emitter is formed on the p+ Si1-xGex layer. An emitter lead electrode 129, which is composed of an n? polysilicon layer 129b containing phosphorus in a concentration equal to or lower than the solid-solubility limit for single-crystal silicon and a n+ polysilicon layer 129a containing phosphorus in a high concentration, is formed on the Si cap layer 111a in a base opening 118. The impurity concentration distribution in the base layer is properly maintained by suppressing the Si cap layer 111a from being doped with phosphorus (P) in an excessively high concentration. The upper portion of the Si cap layer 111a may contain a p-type impurity. The p-type impurity concentration distribution in the base layer of an NPN bipolar transistor is thus properly maintained.Type: GrantFiled: October 26, 2004Date of Patent: May 23, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Teruhito Ohnishi, Akira Asai
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Patent number: 6987072Abstract: A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.Type: GrantFiled: December 13, 2004Date of Patent: January 17, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihiko Kanzawa, Teruhito Ohnishi, Ken Idota, Tohru Saitoh, Akira Asai
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Patent number: 6939772Abstract: A SiGe spacer layer 151, a graded SiGe base layer 152 including boron, and an Si-cap layer 153 are sequentially grown through epitaxial growth over a collector layer 102 on an Si substrate. A second deposited oxide film 112 having a base opening portion 118 and a P+ polysilicon layer 115 that will be made into an emitter connecting electrode filling the base opening portion are formed on the Si-cap layer 153, and an emitter diffusion layer 153a is formed by diffusing phosphorus into the Si-cap layer 153. When the Si-cap layer 153 is grown, by allowing the Si-cap layer 153 to include boron only at the upper part thereof by in-situ doping, the width of a depletion layer 154 is narrowed and a recombination current is reduced, thereby making it possible to improve the linearity of the current characteristics.Type: GrantFiled: July 2, 2004Date of Patent: September 6, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Asai, Teruhito Ohnishi, Takeshi Takagi
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Patent number: 6927118Abstract: The present invention discloses a process of fabricating a semiconductor device comprising the steps of: forming a collector layer of a first conductivity type at a portion of a surface of a semiconductor substrate; forming a collector opening portion in a first insulating layer formed on the semiconductor substrate; epitaxially growing, on the semiconductor substrate of the collector opening portion, a semiconductor layer including a layer of a second conductivity type constituting a base layer; sequentially layering, on the semiconductor substrate, an etching stopper layer against dry etching and a masking layer against wet etching; exposing a part of the etching stopper layer by removing a part of the masking layer by means of dry etching; and by subjecting the exposed etching stopper layer to a wet etching treatment using the remaining masking layer as a mask, forming a base junction opening portion through the etching stopper layer and the masking layer.Type: GrantFiled: October 29, 2003Date of Patent: August 9, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ken Idota, Teruhito Ohnishi, Akira Asai
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Patent number: 6917075Abstract: A semiconductor device and a method of fabricating the same according to this invention are such that: a gate insulator is formed over a predetermined region of a semiconductor substrate; a gate electrode is formed on the gate insulator; source and drain regions respectively formed in portions of the predetermined region that are situated on both sides of the gate electrode in plan view; a body region formed by a region of the predetermined region exclusive of the source and drain regions; and a contact electrically interconnecting the gate electrode and the body region, wherein a portion of the contact which is connected to the gate electrode is formed to intersect the gate electrode in plan view.Type: GrantFiled: January 7, 2004Date of Patent: July 12, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Inoue, Akira Asai, Teruhito Ohnishi, Haruyuki Sorada, Yoshihiro Hara, Takeshi Takagi
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Publication number: 20050092230Abstract: A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.Type: ApplicationFiled: December 13, 2004Publication date: May 5, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yoshihiko Kanzawa, Teruhito Ohnishi, Ken Idota, Tohru Saitoh, Akira Asai