Patents by Inventor Teruhito Oonishi

Teruhito Oonishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6713790
    Abstract: In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: March 30, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Asai, Teruhito Oonishi, Takeshi Takagi, Tohru Saitoh, Yoshihiro Hara, Koichiro Yuki, Katsuya Nozawa, Yoshihiko Kanzawa, Koji Katayama, Yo Ichikawa
  • Publication number: 20020197809
    Abstract: In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.
    Type: Application
    Filed: August 7, 2002
    Publication date: December 26, 2002
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Akira Asai, Teruhito Oonishi, Takeshi Takagi, Tohru Saitoh, Yoshihiro Hara, Koichiro Yuki, Katsuya Nozawa, Yoshihiko Kanzawa, Koji Katayama, Yo Ichikawa
  • Patent number: 6455364
    Abstract: In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: September 24, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Asai, Teruhito Oonishi, Takeshi Takagi, Tohru Saitoh, Yoshihiro Hara, Koichiro Yuki, Katsuya Nozawa, Yoshihiko Kanzawa, Koji Katayama, Yo Ichikawa
  • Patent number: 6273959
    Abstract: There is disclosed a semiconductor device cleaning method involving placing a cleaning solution containing 24 wt. % sulfuric acid, 5 wt. % hydrogen peroxide, 0.02 wt. % hydrogen fluoride, 0.075 wt. % n-dodecylbenzenesulfonic acid, and water into a quartz processing vessel and heating to no more than 100° C. A silicon wafer is immersed into the cleaning solution for 10 minutes and then washed by demineralized water for about 7 minutes. The surfaces of foreign particles on the wafer are etched by hydrogen fluoride, and n-dodecylbenzenesulfonic acid combines with the etched surfaces by sulfate ester bonding. The apparent diameter of the foreign particles increases and the repulsive force caused by zeta potential etc. increases, so that the foreign particles are unlikely to adhere to the surface of the silicon wafer permitting the foreign particles to be easily washed away in a water cleaning step.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: August 14, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Teruhito Oonishi, Ken Idota, Masaaki Niwa, Yoshinao Harada