Patents by Inventor Teruji Inomata

Teruji Inomata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100140796
    Abstract: A manufacturing method of a semiconductor device includes a first to fourth steps. The first step includes a step of determining an UBM (Under Bump Metal) radius of an UBM of a chip. The second step includes a step of determining a first curvature radius of a solder bump formed on the UBM. The third step includes a step of determining a SRO (Solider Resist Opening) radius of a SRO of a substrate such that a ratio of the SRO radius to the UMB radius is in a range from 0.8 to 1.2. The fourth step includes a step of determining a second curvature radius of a spare solder formed on an electrode in the SRO such that the second curvature radius is equal to or more than the first curvature radius.
    Type: Application
    Filed: November 17, 2009
    Publication date: June 10, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Kiminori Ishido, Teruji Inomata
  • Publication number: 20090250826
    Abstract: A process for manufacturing a semiconductor device that inhibits deterioration in the quality of the semiconductor device and a semiconductor device manufactured on such manufacturing process are presented. An operation of determining time-variation of water content in the resin substrate 11 (processing S1); an operation of coupling the semiconductor element 12 onto the resin substrate 11 through a plurality of electroconductive bumps B (processing S3); a first heating operation for controlling a water content of the resin substrate 11 to equal to or lower than 0.02% by heating said resin substrate and said semiconductor element while maintaining the coupling through said bumps (processing S6); and a first heating operation for controlling a water content of the resin substrate 11 to equal to or lower than 0.
    Type: Application
    Filed: March 18, 2009
    Publication date: October 8, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Teruji Inomata
  • Patent number: 7554191
    Abstract: A heatsink plate is to be fixed to a substrate with sufficient strength, so as to prevent the heatsink plate from being stripped off, to thereby secure reliability on the performance of the semiconductor chip. The heatsink plate has both the upper and lower surfaces of the fixing section sandwiched by an adhesive resin. Such structure provides an increased adhesion area between the heatsink plate and the upper surface of the substrate, thereby securing greater fixing strength compared with the conventional structure in which simply the lower surface of the heatsink plate and the upper surface of the substrate are adhered to each other. Accordingly, the heatsink plate can be fixed to the upper surface of substrate with greater strength.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: June 30, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Teruji Inomata, Yoshiaki Sanada
  • Publication number: 20090023252
    Abstract: A heatsink plate is to be fixed to a substrate with sufficient strength, so as to prevent the heatsink plate from being stripped off, to thereby secure reliability on the performance of the semiconductor chip. The heatsink plate has both the upper and lower surfaces of the fixing section sandwiched by an adhesive resin. Such structure provides an increased adhesion area between the heatsink plate and the upper surface of the substrate, thereby securing greater fixing strength compared with the conventional structure in which simply the lower surface of the heatsink plate and the upper surface of the substrate are adhered to each other. Accordingly, the heatsink plate can be fixed to the upper surface of substrate with greater strength.
    Type: Application
    Filed: September 22, 2008
    Publication date: January 22, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Teruji Inomata, Yoshiaki Sanada
  • Publication number: 20080251913
    Abstract: In one embodiment of the present invention, there is provided a semiconductor device including a first semiconductor element mounted, through flip-chip bonding, on the element mounting surface of a first wiring substrate, and a resin layer that coats substantially the entire element mounting surface of the first wiring substrate. The first semiconductor element has two opposite surfaces. One surface faces the element mounting surface of the first wiring substrate, and the other surface is not coated by the resin layer.
    Type: Application
    Filed: September 7, 2007
    Publication date: October 16, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Teruji INOMATA
  • Patent number: 7370786
    Abstract: Disclosed are a bonding method for a semiconductor chip, which employs an ultrasonic bonding scheme that prevents wear-out of the top surface of a mount tool and ensures both high reliability and high productivity, and a bonding apparatus which is used to carry out the method. The bonding apparatus and method are provided with means for suppressing generation of a sliding friction. The apparatus and method execute a bonding process by controlling vibration-axial directional holding force and inertial force based on information given from control management means to thereby maintain a relationship of (vibration-axial directional holding force)>(die shear strength)+(inertial force) while applying an ultrasonic vibration to a region which is subjected to bonding.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: May 13, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Yoichiro Kurita, Jun Nogawa, Masato Maeda, Teruji Inomata
  • Publication number: 20070228115
    Abstract: A method of manufacturing an electronic component which can reduce voids in a solder and can reliably melt the solder is provided. The method of manufacturing an electronic component including a member (substrate 1) having a metal junction (electrode 11) includes: the step of supplying a solder 5 containing a solvent, a resin component, an activator, and a brazing filler metal to the junction (electrode 11); the first heating step in which a first heating process to the solder 5 is performed and the solder 5 is kept at a first heating temperature for a predetermined period of time; the second heating step in which a second heating process to the solder 5 is preformed and the solder 5 is kept at a second heating temperature higher than the first heating temperature for a predetermined period of time to vaporize the solvent and the resin component; and the third heating step in which a third heating process to the solder 5 is performed and the solder 5 is melted.
    Type: Application
    Filed: October 4, 2006
    Publication date: October 4, 2007
    Inventors: Teruji Inomata, Masatoshi Sugiura
  • Publication number: 20070152322
    Abstract: A heatsink plate is to be fixed to a substrate with sufficient strength, so as to prevent the heatsink plate from being stripped off, to thereby secure reliability on the performance of the semiconductor chip. The heatsink plate has both the upper and lower surfaces of the fixing section sandwiched by an adhesive resin. Such structure provides an increased adhesion area between the heatsink plate and the upper surface of the substrate, thereby securing greater fixing strength compared with the conventional structure in which simply the lower surface of the heatsink plate and the upper surface of the substrate are adhered to each other. Accordingly, the heatsink plate can be fixed to the upper surface of substrate with greater strength.
    Type: Application
    Filed: January 3, 2007
    Publication date: July 5, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Teruji Inomata, Yoshiaki Sanada
  • Publication number: 20060011706
    Abstract: Disclosed are a bonding method for a semiconductor chip, which employs an ultrasonic bonding scheme that prevents wear-out of the top surface of a mount tool and ensures both high reliability and high productivity, and a bonding apparatus which is used to carry out the method. The bonding apparatus and method are provided with means for suppressing generation of a sliding friction. The apparatus and method execute a bonding process by controlling vibration-axial directional holding force and inertial force based on information given from control management means to thereby maintain a relationship of (vibration-axial directional holding force)>(die shear strength)+(inertial force) while applying an ultrasonic vibration to a region which is subjected to bonding.
    Type: Application
    Filed: July 15, 2005
    Publication date: January 19, 2006
    Inventors: Yoichiro Kurita, Jun Nogawa, Masato Maeda, Teruji Inomata
  • Patent number: 6932262
    Abstract: Disclosed are a bonding method for a semiconductor chip, which employs an ultrasonic bonding scheme that prevents wear-out of the top surface of a mount tool and ensures both high reliability and high productivity, and a bonding apparatus which is used to carry out the method. The bonding apparatus and method are provided with means for suppressing generation of a sliding friction. The apparatus and method execute a bonding process by controlling vibration-axial directional holding force and inertial force based on information given from control management means to thereby maintain a relationship of (vibration-axial directional holding force)>(die shear strength)+(inertial force) while applying an ultrasonic vibration to a region which is subjected to bonding.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: August 23, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Yoichiro Kurita, Jun Nogawa, Masato Maeda, Teruji Inomata
  • Patent number: 6814274
    Abstract: When viewed in a first direction, a cross section of a pressing surface of the bonding tool for pressing the inner leads is flat and extends uniformly over a range longer than the interval between every two electrode pads. When viewed in a second direction orthogonal to the first direction, and when the inner leads are pressed to the electrode pads by virtue of a predetermined pressing force, the length of a pressing area having a pressing force acting between the inner leads and the electrode pads is shorter than the length of each electrode pad.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: November 9, 2004
    Assignee: NEC Electronics Corporation
    Inventors: Yoichiro Kurita, Teruji Inomata
  • Publication number: 20040214406
    Abstract: Disclosed are a bonding method for a semiconductor chip, which employs an ultrasonic bonding scheme that prevents wear-out of the top surface of a mount tool and ensures both high reliability and high productivity, and a bonding apparatus which is used to carry out the method. The bonding apparatus and method are provided with means for suppressing generation of a sliding friction.
    Type: Application
    Filed: July 25, 2003
    Publication date: October 28, 2004
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yoichiro Kurita, Jun Nogawa, Masato Maeda, Teruji Inomata
  • Publication number: 20030010812
    Abstract: When viewed in a first direction, a cross section of a pressing surface of the bonding tool for pressing the inner leads is flat and extends uniformly over a range longer than the interval between every two electrode pads. When viewed in a second direction orthogonal to the first direction, and when the inner leads are pressed to the electrode pads by virtue of a predetermined pressing force, the length of a pressing area having a pressing force acting between the inner leads and the electrode pads is shorter than the length of each electrode pad.
    Type: Application
    Filed: June 24, 2002
    Publication date: January 16, 2003
    Inventors: Yoichiro Kurita, Teruji Inomata
  • Publication number: 20020106903
    Abstract: A manufacturing method of a semiconductor device in which wire connection means is connected to an electrode formed on a surface of an IC and made of Cu or a material mainly containing Cu, comprises an oxide film removal treatment step of applying a Cu oxide film removal treatment to the electrode, and a supersonic bonding step of bonding the wire connection means with supersonic to the electrode after the oxide film removal treatment step.
    Type: Application
    Filed: February 5, 2002
    Publication date: August 8, 2002
    Applicant: NEC CORPORATION
    Inventors: Yoichiro Kurita, Teruji Inomata