Abstract: The prior D.D.A. (Digital Differential Analyzer) having an integrand register, a remainder register and an adder for pulse interpolation has been improved by attaching some new units to the same, including a counter for counting the reference instruction pulses, a register for storing the content of the counter, and a multiplier for providing the product of the content of said register and the content of said integrand register. The product provided by the multiplier instead of the output of the integrand register, is applied to one input of the adder, the other input of which receives the output of said remainder register. Thus, the interpolation calculation has only to be performed once in every several periods of the instruction pulses, therefore, a slow speed digital element can be utilized for high speed instruction calculation.

Abstract: A D.D.A. (Digital Differential Analyzer) for pulse interpolation having a memory counter with more than two bit positions for counting the number (m) of input instruction pulses in each interpolation cycle, a second counter for receiving the content of the memory counter, and an auxiliary adder for obtaining m multiple of the content of the integrand register in the D.D.A. system. The output of the auxiliary adder instead of the output of the integrand register is applied to an interpolation adder. Thus, the pulse interpolator can operate correctly even when more than two input instruction pulses are generated within a single interpolation cycle.