Abstract: A person who would like to cancel read-protection of ROM data inputs an “address,” an “information length,” and an “input information part.” The input information part should be a part of a data file stored in the ROM. The input address corresponds to the starting address of the information part in the ROM. The input information length is the length of the input information part. A ROM-data read-control circuit reads a stored information part with the input information length from an area or areas in the ROM with the input starting address. Next, the ROM-data read-control circuit compares the stored information part with the input information part. The ROM-data read-control circuit cancels the read-protection when the input information part coincides with the stored information part.

Abstract: A ROM data verification circuit has a DMAC (2) for reading out data stored in the ROM (1) when a CPU (3) abandons to use an address bus (5) and a data bus (6), for dividing the data read into a plurality of divided data, and for outputting the divided data into a plurality of output ports (4) designated by addresses generated by the DMAC (2).

Abstract: A ROM data read protect circuit according to the present invention comprises a non-volatile memory that stores a data for allowing or inhibiting reading of the ROM data and a logic circuit for control for controlling allowing or inhibiting of an operation for reading of data in a ROM according to the data stored in the non-volatile memory. When "0" is written in a first storage area of the non-volatile memory reading of the ROM data is inhibited, and when "0" is written in a second storage area of the non-volatile memory reading of the ROM data is allowed. A data can be written anytime in the first storage area but data can not be deleted from the first storage, so that the read inhibit mode is always effected in the initial state. A data can be written in the second storage area only when specific setting is executed but can not be deleted from the second storage.

Abstract: Programmable logical blocks (3a to 3c) selected from a block library including information of a plurality of types of programmable logical blocks are disposed in a core region of a semiconductor integrated circuit (100). The degree of freedom of designing a field programmable gate array (FPGA) and the degree of integration are increased. A logic LSI is permitted to have redundancy to flexibly cope with design changes. This affords reduction in develop period and develop costs.

Abstract: A register circuit an arithmetic circuit a register circuit and a logic circuit form a bit slice cell corresponding to a path of propagation connecting the circuits in this order. Similarly, an arithmetic circuit register circuits and a logic circuit form a bit slice cell and an arithmetic circuit register circuits and a logic circuit form a bit slice cell. The bit slice cells are arranged generally in parallel to form a bit slice circuit which prevents redundant lines for connecting the functional circuits, whereby the bit slice circuit is developed in a short period without a decreased degree of integration and prolonged delay time.

Abstract: In designing a layout of a semiconductor integrated circuit device having a large scale circuit block and logic circuit elements provided together, a power supply connecting line is formed rectilinearly to increase the integration density, reduce power supply noise and achieve automation of layout and interconnection. The semiconductor integrated circuit device includes one large scale circuit block and a plurality of logic circuit elements. VDD and GND annular power supply interconnecting lines are provided to surround the large scale circuit block. The annular power supply interconnecting lines extending in the lateral direction are divided into two lines to be disposed, respectively. Connection of the logic circuit elements and the annular power supply interconnecting lines are made by rectilinear VDD and GND power supply branch interconnecting lines.