Abstract: A method for analyzing timing in a semiconductor integrated circuit device with multi-corner conditions including a best-case corner condition and a worst-case corner condition. The best-case corner condition and the worst-case corner condition each include a temperature condition, with each temperature condition being a high temperature condition or a low temperature condition. The method includes storing in a temperature characteristic coefficient table a temperature characteristic coefficient for each of temperature-reversed corner conditions that are generated by selectively reversing the temperature conditions of the best-case corner condition and the worst-case corner condition, and performing timing analysis under said temperature-reversed corner conditions based on a gate delay and net delay calculated under the best-case corner condition and the worst-case corner condition and the temperature characteristic coefficient.

Abstract: A method for correcting a timing error in an integrated circuit that includes a plurality of layout blocks with identical configurations in the same hierarchical layer. The method includes matching the tolerance for when a timing error occurs for a cell in each layout block with a worst condition of one of the corresponding cells in the layout blocks, and inserting a timing adjustment cell within a range of the matched tolerance of each cell to adjust the timing error. This method ensures the correction of hold errors and setup errors in an integrated circuit designed with a hierarchical design technique.

Abstract: A method for analyzing timing in a semiconductor integrated circuit device with multi-corner conditions including a best-case corner condition and a worst-case corner condition. The best-case corner condition and the worst-case corner condition each include a temperature condition, with each temperature condition being a high temperature condition or a low temperature condition. The method includes storing in a temperature characteristic coefficient table a temperature characteristic coefficient for each of temperature-reversed corner conditions that are generated by selectively reversing the temperature conditions of the best-case corner condition and the worst-case corner condition, and performing timing analysis under said temperature-reversed corner conditions based on a gate delay and net delay calculated under the best-case corner condition and the worst-case corner condition and the temperature characteristic coefficient.

Abstract: A method for correcting a timing error in an integrated circuit that includes a plurality of layout blocks with identical configurations in the same hierarchical layer. The method includes matching the tolerance for when a timing error occurs for a cell in each layout block with a worst condition of one of the corresponding cells in the layout blocks, and inserting a timing adjustment cell within a range of the matched tolerance of each cell to adjust the timing error. This method ensures the correction of hold errors and setup errors in an integrated circuit designed with a hierarchical design technique.

Abstract: A semiconductor device having multiple memory circuits of varying sizes includes scan test circuitry that enables the memories to be simultaneous loaded with pattern data and tested. A first memory circuit has a first memory, a first address scan chain that receives serial scan-in address data and generates a first address signal, and a first data scan chain that receives serial scan-in data and generates a first data input signal. A second memory circuit has a second memory, a second address scan chain that receives the serial scan-in address data and generates a second address signal, and a second data scan chain that receives the serial scan-in data and generates a second data input signal.

Abstract: A system and apparatus for using hierarchically organized data to design semiconductor integrated circuits is herein disclosed wherein a plurality of macros and circuit logic cells containing circuit component parameter information are cross referenced using two types of pointers. An intermediate table 27 in a logic development file 5 stores information relating to a general controlling macro "CHIP", user defined macros A, B, and also stores the parameter information relating to every macro. A cell table 28 stores circuit cells C, D, E, F. The macro "CHIP" A, B, and cells, and the macro and cell are cross referenced by multi-table and an identical table pointer.