Abstract: According to an embodiment(s), a current detection circuit has first and second main electrodes, a vertical structure output transistor that includes a first control electrode where a control signal is supplied thereto, a third main electrode that is connected to the first main electrode, a second control electrode that is connected to the first control electrode, and a vertical structure detection transistor that has a fourth main electrode. The current detection circuit has a voltage supply circuit that supplies a divided voltage of a voltage between the first and second main electrodes to the fourth main electrode.

Abstract: According to an embodiment(s), a current detection circuit has first and second main electrodes, a vertical structure output transistor that includes a first control electrode where a control signal is supplied thereto, a third main electrode that is connected to the first main electrode, a second control electrode that is connected to the first control electrode, and a vertical structure detection transistor that has a fourth main electrode. The current detection circuit has a voltage supply circuit that supplies a divided voltage of a voltage between the first and second main electrodes to the fourth main electrode.

Abstract: A D-class amplifier includes: a bridge circuit adapted to drive an inductive load; a power supply voltage detection section outputting a quantized power supply voltage signal indicating a power supply voltage fed to the bridge circuit; and a gain-controlled PWM section adjusting a gain in response to the quantized power supply voltage signal, amplifying the input signal in response to the gain, generating a PWM signal from the amplified input signal, and feeding the PWM signal to the bridge circuit. The power supply voltage detection section includes: an error integration section generating a quantized signal by integrating a difference between the power supply voltage and the quantized power supply voltage signal; and a digital filter removing high frequency components of the quantized signal to output the quantized power supply voltage signal. The gain-controlled PWM section controls the gain such that variations of the power supply voltage are cancelled.

Abstract: A D-class amplifier includes: a bridge circuit adapted to drive an inductive load; a power supply voltage detection section outputting a quantized power supply voltage signal indicating a power supply voltage fed to the bridge circuit; and a gain-controlled PWM section adjusting a gain in response to the quantized power supply voltage signal, amplifying the input signal in response to the gain, generating a PWM signal from the amplified input signal, and feeding the PWM signal to the bridge circuit. The power supply voltage detection section includes: an error integration section generating a quantized signal by integrating a difference between the power supply voltage and the quantized power supply voltage signal; and a digital filter removing high frequency components of the quantized signal to output the quantized power supply voltage signal. The gain-controlled PWM section controls the gain such that variations of the power supply voltage are cancelled.

Abstract: Class D amplifier is resistant to interferences. Binary output signals y1 and y2, are generated from input signal s1, delivered to input terminal IN, to drive a load connected across output terminals OUTP and OUTN. Pulse generating circuit 10 generates a pulse width modulated pulse signal y0 from input signal s1, inverted signal of the output signal y1 and output signal y2. Differential pulse generating circuit 14 receives pulse signal y0 and inverts low and high levels of pulse signal y0, while shifting the resulting signal by half period from the pulse signal y0, to generate a pulse signal y3. Pulse amplifier 11a receives pulse signal y0 and generates output signal y1 supplied to output terminal OUTP. Pulse amplifier 11b receives pulse signal y3 and generates output signal y2 delivered to output terminal OUTN.

Abstract: Class D amplifier is resistant to interferences. Binary output signals y1 and y2, are generated from input signal s1, delivered to input terminal IN, to drive a load connected across output terminals OUTP and OUTN. Pulse generating circuit 10 generates a pulse width modulated pulse signal y0 from input signal s1, inverted signal of the output signal y1 and output signal y2. Differential pulse generating circuit 14 receives pulse signal y0 and inverts low and high levels of pulse signal y0, while shifting the resulting signal by half period from the pulse signal y0, to generate a pulse signal y3. Pulse amplifier 11a receives pulse signal y0 and generates output signal y1 supplied to output terminal OUTP. Pulse amplifier 11b receives pulse signal y3 and generates output signal y2 delivered to output terminal OUTN.