Patents by Inventor Terunari KANO

Terunari KANO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090294155
    Abstract: According to one embodiment, there is provided a flexible printed circuit board including a base layer, a signal layer formed on a surface of the base layer, a cover layer covering the signal layer, a connecting pattern portion formed in the signal layer, an opening formed in the cover layer and surrounds periphery of the connecting pattern portion, a conductive shield material covering the cover layer in which part of the conductive shield material fills the opening, thereby adhering to an upper face and sides of the connecting pattern portion, and a protective layer covering the conductive shield material.
    Type: Application
    Filed: May 29, 2009
    Publication date: December 3, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daigo SUZUKI, Kiyomi MURO, Terunari KANO, Gen FUKAYA
  • Publication number: 20080179079
    Abstract: According to one embodiment, there is provided a printed-wiring board in which a composite board is formed to have rigid portions and a bending portion, wherein the bending portion includes linear protrusions each formed with solder resist having a bending resistance property.
    Type: Application
    Filed: October 24, 2007
    Publication date: July 31, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Norihiro Ishii, Sadahiro Tamai, Terunari Kano
  • Publication number: 20080121422
    Abstract: According to one embodiment, there is provided a multilayered printed-wiring board, which includes a first wiring layer and a second wiring layer each of which forms an outer layer, a plurality of third wiring layers which are disposed between the first wiring layer and the second wiring layer to form an inner layer structure, first vias disposed in the first and second wiring layers, second vias disposed in the third wiring layers and connected to the first vias, and a third via disposed in an innermost third wiring layer in the inner layer structure and connected to the second vias, the third via having a diameter larger than those of the first and second vias.
    Type: Application
    Filed: November 29, 2007
    Publication date: May 29, 2008
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Jun Karasawa, Terunari Kano