Patents by Inventor Terunari Takano

Terunari Takano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6777313
    Abstract: Bumps electrically connected to elements are formed on the main surface of a wafer on which the elements are formed and grooves with depths which do not reach the back surface of the wafer are formed in the wafer on the main surface side thereof along dicing lines or chip dividing lines of the wafer. The bump forming surface of the wafer is coated with a seal member and a back side grinding process for the wafer is performed to make the wafer thin, and at the same time, divide the wafer into individual chips. One of the chips which are discretely divided by performing the back side grinding process is picked up, the bumps of the picked-up chip are bonded and mounted to and on a base board, and at the same time, the seal member is melted for sealing.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: August 17, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Takyu, Mika Kiritani, Tetsuya Kurosawa, Terunari Takano
  • Patent number: 6545348
    Abstract: A first interconnection pattern having a comb shape is formed around a semiconductor chip on a package body. A second interconnection pattern having a comb shape is formed around the first interconnection pattern. The projections of the first interconnection pattern are engaged with the projections of the second interconnection pattern. The distances between those two groups of projections and the bonding pads of the semiconductor chip are set nearly equal to each other.
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: April 8, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Terunari Takano
  • Publication number: 20030017663
    Abstract: Bumps electrically connected to elements are formed on the main surface of a wafer on which the elements are formed and grooves with depths which do not reach the back surface of the wafer are formed in the wafer on the main surface side thereof along dicing lines or chip dividing lines of the wafer. The bump forming surface of the wafer is coated with a seal member and a back side grinding process for the wafer is performed to make the wafer thin, and at the same time, divide the wafer into individual chips. One of the chips which are discretely divided by performing the back side grinding process is picked up, the bumps of the picked-up chip are bonded and mounted to and on a base board, and at the same time, the seal member is melted for sealing.
    Type: Application
    Filed: July 3, 2002
    Publication date: January 23, 2003
    Inventors: Shinya Takyu, Mika Kiritani, Tetsuya Kurosawa, Terunari Takano
  • Patent number: 6326243
    Abstract: A semiconductor chip having a plurality of electrodes on its surface is fixed onto a die pad. The leads are spaced away from the die pad and connected to the electrodes of the semiconductor chip by means of a TAB tape. The die pad is substantially equal in size to the insulation film of the TAB tape. The die pad has a plurality of resin circulating holes around the semiconductor chip. The resin circulating holes are arranged such that a fluid resin sufficiently flows into a narrow area between the TAB tape and die pad. On the die pad, portions each between adjacent resin circulating holes serves as heat conducting paths. The heat generated from the semiconductor chip is transmitted to the entire region of the die pad through the heat conducting paths and then radiated outside.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: December 4, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhito Suzuya, Morihiko Ikemizu, Terunari Takano, Kenji Uehara, Akito Yoshida
  • Patent number: 5753969
    Abstract: A semiconductor chip having a plurality of electrodes on its surface is fixed onto a die pad. The leads are spaced away from the die pad and connected to the electrodes of the semiconductor chip by means of a TAB tape. The die pad is substantially equal in size to the insulation film of the TAB tape. The die pad has a plurality of resin circulating holes around the semiconductor chip. The resin circulating holes are arranged such that a fluid resin sufficiently flows into a narrow area between the TAB tape and die pad. On the die pad, portions each between adjacent resin circulating holes serves as heat conducting paths. The heat generated from the semiconductor chip is transmitted to the entire region of the die pad through the heat conducting paths and then radiated outside.
    Type: Grant
    Filed: August 14, 1996
    Date of Patent: May 19, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhito Suzuya, Morihiko Ikemizu, Terunari Takano, Kenji Uehara, Akito Yoshida