Abstract: A semiconductor device includes an external terminal, an input buffer having an input terminal connected to the external terminal, a voltage generating circuit configured to generate a test voltage supplied to the input terminal, and a control circuit configured to determine whether the input buffer is deteriorated based on the test voltage supplied to the input terminal and an output level of the input buffer responding to the test voltage.

Abstract: A semiconductor device includes an external terminal, an input buffer having an input terminal connected to the external terminal, a voltage generating circuit configured to generate a test voltage supplied to the input terminal, and a control circuit configured to determine whether the input buffer is deteriorated based on the test voltage supplied to the input terminal and an output level of the input buffer responding to the test voltage.

Abstract: A signal processing device includes an oscillation circuit, a protection target circuit, a delay time detection circuit, and a clock control circuit. The oscillation circuit receives the frequency control signal and generates a clock signal having a frequency corresponding to the frequency control signal. According to the above-mentioned configuration, even when a delay failure due to aging occurs in the signal processing device, it is possible to prevent a malfunction.

Abstract: The semiconductor device according to this disclosure includes an analog input terminal, an amplifier circuit, a sample-and-hold circuit, an analog input switch connected between the analog input terminal and the input terminal of the amplifier circuit, a control switch connected between the output terminal of the amplifier circuit and the input terminal of the sample-and-hold circuit, a comparison circuit connected to the output terminal of the sample-and-hold circuit, an analog-to-digital converter connected to the comparator circuit, a control circuit, and a signal conversion circuit for converting the first control signal from the control circuit into a second control signal. The analog input switch is turned on during the activation level of the second control signal. The period of the activation level of the second control signal is longer than that of the first control signal to reduce a conversion error of an analog-to-digital conversion circuit.

Abstract: The semiconductor device according to this disclosure includes an analog input terminal, an amplifier circuit, a sample-and-hold circuit, an analog input switch connected between the analog input terminal and the input terminal of the amplifier circuit, a control switch connected between the output terminal of the amplifier circuit and the input terminal of the sample-and-hold circuit, a comparison circuit connected to the output terminal of the sample-and-hold circuit, an analog-to-digital converter connected to the comparator circuit, a control circuit, and a signal conversion circuit for converting the first control signal from the control circuit into a second control signal. The analog input switch is turned on during the activation level of the second control signal. The period of the activation level of the second control signal is longer than that of the first control signal to reduce a conversion error of an analog-to-digital conversion circuit.

Abstract: A signal processing device includes an oscillation circuit, a protection target circuit, a delay time detection circuit, and a clock control circuit. The oscillation circuit receives the frequency control signal and generates a clock signal having a frequency corresponding to the frequency control signal. According to the above-mentioned configuration, even when a delay failure due to aging occurs in the signal processing device, it is possible to prevent a malfunction.

Abstract: In a semiconductor device of related art, the degree of freedom when using one pad with plural functions has been disadvantageously low. A semiconductor device has an internal logic circuit, a regulator circuit, and an interface circuit, and the regulator circuit and the interface circuit are coupled to one shared pad. In the case where a driving transistor of the regulator circuit is controlled to be in a conductive state, the shared pad is used as a terminal to which an input voltage of the regulator circuit is input. In the case where the driving transistor of the regulator circuit is controlled to be in a disconnected state, the shared pad is used as an input/output terminal of the interface circuit.

Abstract: In a semiconductor device of related art, the degree of freedom when using one pad with plural functions has been disadvantageously low. A semiconductor device has an internal logic circuit, a regulator circuit, and an interface circuit, and the regulator circuit and the interface circuit are coupled to one shared pad. In the case where a driving transistor of the regulator circuit is controlled to be in a conductive state, the shared pad is used as a terminal to which an input voltage of the regulator circuit is input. In the case where the driving transistor of the regulator circuit is controlled to be in a disconnected state, the shared pad is used as an input/output terminal of the interface circuit.

Abstract: A constant voltage generation circuit in which a charging circuit (T1) connected to one side of resistors (LR2 to LR5) rapidly supplies a higher voltage, that is further higher than any voltage generated at each of the resistors (LR2 to LR5), to the output terminal (OT) during a desired time period when one of switches (SW2 to SW4) turns on to provide the voltage to be switched to the output terminal (OT) and when the voltage to be switched is higher than a current voltage of the output terminal (OT). Furthermore, in the circuit, a charging circuit (T2 ) connected to other side of resistors (LR2 to LR5) rapidly supplies a lower voltage, that is further lower than any voltage generated at each of the resistors (LR2 to LR5), to the output terminal (OT) during a desired time period when one of switches (SW2 to SW4) turns on to provide the voltage to be switched to the output terminal (OT) and when the voltage to be switched is lower than a current voltage of the output terminal (OT).

Abstract: Provided is a data read circuit that can execute data reading under a proper reference voltage in the event that element characteristics have been changed due to aged deterioration. When a sample memory cell (10a) is selected, a memory transistor (26a) in which no electrons are injected into its floating gate, enters ON state. At this time, a voltage (V.sub.22) is inputted to an input terminal (22) of a sense amplification (18), and a control circuit (13) detects the voltage (V.sub.22) to store it as a digital signal. On the other hand, when a sample memory cell (10b) is selected, a memory transistor (26b) in which electrons are injected into its floating gate, does not enter ON state. As a result, a voltage (V.sub.11) is inputted as it is, to the input terminal (22). The control circuit (13) detects the voltage (V.sub.11) to store it as a digital signal. Based on the two digital signals, the control circuit (13) sets a reference voltage (V.sub.

Abstract: A harmonic of a resonance frequency of an oscillator, which occurs at the initial stage of the oscillation of the oscillator, is divided to obtain a pulse to be used as a clock for the operation of a microcomputer before the oscillation is stabilized. Thus, the invention provides a clock generation circuit and a microcomputer which shorten a time period required from the application of power or the clock halt state to the start of the operation of the microcomputer.