Patents by Inventor Teruo ATSUMI

Teruo ATSUMI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967463
    Abstract: A ceramic electronic device includes a multilayer structure in which each of a plurality of dielectric layers of which a main component is ceramic and each of a plurality of internal electrode layers having pores are alternately stacked. A continuity modulus of at least one of the plurality of internal electrode layers is 80% or less. An average pore diameter of the pores of the at least one of the plurality of internal electrode layers is equal to or less than each thickness of the plurality of dielectric layers.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: April 23, 2024
    Assignee: TAIYO YUDEN CO., LTD.
    Inventor: Teruo Atsumi
  • Patent number: 11830674
    Abstract: A ceramic electronic device includes a multilayer chip in which a plurality of dielectric layers and a plurality of internal electrode layers are stacked. The plurality of internal electrode layers include Au. Each of the plurality of internal electrode layers includes an Au-containing layer of which an Au concentration with respect to all detected elements is 5 at % or more, on an interface between the each of the plurality of internal electrode layers and a dielectric layer next to the each of the plurality of internal electrode layers. A relationship of C?500×t/T is satisfied when a thickness of the each of the plurality of internal electrode layers is T nm, a thickness of the Au-containing layer is t nm, and an Au concentration with respect to a total of Ni and Au in a whole of the each of the plurality of internal electrode layers is C at %.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: November 28, 2023
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Hidetoshi Masuda, Minoru Ryu, Teruo Atsumi
  • Publication number: 20220415574
    Abstract: A ceramic electronic device includes a multilayer structure in which each of a plurality of dielectric layers of which a main component is ceramic and each of a plurality of internal electrode layers having pores are alternately stacked. A continuity modulus of at least one of the plurality of internal electrode layers is 80% or less. An average pore diameter of the pores of the at least one of the plurality of internal electrode layers is equal to or less than each thickness of the plurality of dielectric layers.
    Type: Application
    Filed: May 27, 2022
    Publication date: December 29, 2022
    Applicant: TAIYO YUDEN CO., LTD.
    Inventor: Teruo ATSUMI
  • Publication number: 20220384109
    Abstract: A ceramic electronic device includes a multilayer chip in which a plurality of dielectric layers and a plurality of internal electrode layers are stacked. The plurality of internal electrode layers include Au. Each of the plurality of internal electrode layers includes an Au-containing layer of which an Au concentration with respect to all detected elements is 5 at % or more, on an interface between the each of the plurality of internal electrode layers and a dielectric layer next to the each of the plurality of internal electrode layers. A relationship of C?500×t/T is satisfied when a thickness of the each of the plurality of internal electrode layers is T nm, a thickness of the Au-containing layer is t nm, and an Au concentration with respect to a total of Ni and Au in a whole of the each of the plurality of internal electrode layers is C at %.
    Type: Application
    Filed: April 25, 2022
    Publication date: December 1, 2022
    Inventors: Hidetoshi MASUDA, Minoru RYU, Teruo ATSUMI
  • Publication number: 20210035744
    Abstract: A multilayer ceramic device includes a ceramic main body including a plurality of internal electrodes laminated in a first direction, the ceramic main body having a pair of end surfaces respectively facing a second direction perpendicular to the first direction and a direction opposite to the second direction; a pair of protective layers covering respective entire areas of said pair of end surfaces, the protective layers each including at least one of Al, Si, Cr, Zn, Ga, Ge, In, Sn, W, Pt, Au and Bi as a main component thereof; and a pair of external electrodes respectively covering the pair of end surfaces through the pair of protective layers, respectively.
    Type: Application
    Filed: July 31, 2020
    Publication date: February 4, 2021
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Teruo ATSUMI, Yoshiki IWAZAKI