Abstract: Display data is read out from a display memory in parallel, and is temporarily held in a first shift register located near to the display memory. The display data is serially read out and transferred from the first shift register in one bit unit to a second shift register located near to an display data latch, in synchronism with a shift clock signal outputted from a shift clock controlling circuit. The display data held in the second shift register is outputted in parallel to the display data latch in accordance with a display data read signal. Thus, it is possible to reduce the increase of the number of the wiring lines extending from the display memory to the display data latch, as well as the increase of the chip area, both of which would be caused by the increase of the display segments. It is also possible to reduce the limitations related to the arrangement of the interior of the microcomputer.