Abstract: When burst traffic causes a packet to overflow or to be ready to overflow from a queue, a packet relay apparatus mirrors only the packets to be accumulated in that queue. An outgoing queue management unit copies a packet into a queue in an outgoing queue list and then obtains the length of the queue (step 272). If the queue length is greater than a mirroring starting threshold, the value of the mirroring on/off flag in the corresponding queue entry is changed to ON (step 275). If the queue length is smaller than a mirroring stopping threshold, the value of the flag is changed to OFF (step 274). After the queue length exceeds the mirroring starting threshold until the queue length becomes smaller than the mirroring stopping threshold, only the packets to be output to that queue are mirrored.

Abstract: Network relay arrangements including: multiple ports; MAC address storage; flooding indication storage; plane number management storage; table manager; and frame processor. The table manager: utilizes the plane number management storage to specify current identification information being currently used and next identification information to be used next, with regard to a preset element of the key item for identifying a target of deletion of the information of correlating the transmit port to the MAC address from the MAC address storage; sets the requirement of the flooding operation in registry of a certain information group in the flooding indication storage having the preset element and being correlated to the current identification information; and sets the non-requirement of the flooding operation in registry of a certain information group in the flooding indication storage having the preset element and being correlated to the next identification information.

Abstract: A network system includes: a core switch; and an edge switch. The edge switch includes: a join message identification unit; and a marking unit. The join message identification unit identifies a join message from among MAC frames from the user network. The marking unit marks mark information to a header of a MAC-in-MAC frame in which the identified join message is encapsulated. The core switch includes: a plurality of input/output ports; a mark identification unit; and a port setup unit. The mark identification unit identifies a MAC-in-MAC frame to whose a header the mark information is marked. The port setup unit associates a multicast group of a join message which is encapsulated in the identified MAC-in-MAC frame, with an input/output port to which the identified MAC-in-MAC frame is input.

Abstract: A network system forms a computer network, and includes: a collecting unit; a calculating unit; and a display unit. The collecting unit collects power consumption information from a connecting device. The power consumption information shows power consumption of the connecting device. The calculating unit calculates power consumption of the computer network based on the collected power consumption information. The calculated power consumption is itemized into constituent units based on a configuration of the computer network. The display unit displays the calculated power consumption.

Abstract: The communication device has a frame transfer unit that executes frame transfer via the first communication link and the second communication link, a link confirmation frame sending unit, and a return link confirmation frame monitoring unit. The link confirmation frame sending unit causes the frame transfer processing unit to send a link confirmation frame for use in confirming a normal link status via the first communication link from the communication device to the counterpart communication device. The return link confirmation frame monitoring unit performs fault detection of the first and second communication links by monitoring a return link confirmation frame which is to be returned from the counterpart communication device to the communication device via the second communication link when the counterpart communication device receives the link confirmation frame via the first communication link.

Abstract: A packet transfer apparatus includes a data analyzing unit, a memory control unit, and a control unit that holds a copy condition table and has a control information comparing unit. The data analyzing unit refers to a header of a received packet to analyze control information and transmits an analysis result to the control unit. The control unit searches the copy condition table on the basis of the analysis result and transmits a search result to the memory control unit. The memory control unit generates a record of a copy packet whose packet length is shortened in a memory calling management table on the basis of the search result.

Abstract: A switching system includes a data collection device, one or more switching devices. The data collection device is for collection of first data subject to specific processing. The switching devices directly or indirectly connected to the data collection device. At least one of the switching devices includes a determination module that determines whether received data is the first data or is second data which is not subject to the specific processing, and a marking module that puts first marking on the received data determined to be the first data. The switching devices respectively includes a transferring processor that executes a first transfer process for sending the received data to the data collection device when the received data has the first marking, and a second transfer process that sends the received data to the specified destination when the received data does not have the first marking.

Abstract: A packet receiving circuit splits the packet received from a transmission channel into a fixed length of cells and outputs the cells, a search key extracting circuit extracts a predetermined search key from the above-mentioned cells, a CAM performs retrieval based on the above-mentioned search key and outputs a memory address corresponding to the search key, a matching entry address receiving and associative data address transmitting circuit calculates the memory address of an associative data memory based on the above-mentioned memory address and outputs the information stored in the associative data memory as associative data, a search result (associative data) receiving circuit receives the above-mentioned associative data and performs header updating and destination address of the above-mentioned cells, and a packet transmitting circuit outputs the above-mentioned cells in the form of a packet to a transmission channel.

Abstract: A bus switch system having an adapter, a first input and first output register in cascade connection on a data transferring bus of bus switch that comprise input and output shift registers. There is also a bridge, the second input and second output registers are in a cascade connection on the first data transferring bus form a shift register. This allows data to be transferred to an adjacent adapter at one clock cycle, thereby the data transfer is made faster. The data transfer on the first and second data transferring buses is conducted in one direction and input/output control is optimally conducted by first and second control means so that switch control in data transfer is made easier.

Abstract: A content-addressable memory device with multiple WORD lines has: a first memory block to store whether there is a hit during current time period; a second memory block to store whether there is a hit during a period preceding the current time period, the first and second memory blocks being provided for each WORD line; and elements for selecting a WORD line to determine a WORD line to be aged out according to values stored in the first and second memory blocks.

Abstract: A content-addressable memory device with multiple WORD lines has: a first memory block to store whether there is a hit during current time period; a second memory block to store whether there is a hit during a period preceding the current time period, the first and second memory blocks being provided for each WORD line; and means of selecting a WORD line to determine a WORD line to be aged out according to values stored in the first and second memory blocks.

Abstract: Data transfer mode between a plurality of circuit mod modules connected to a data bus is dynamically switched between a time division, space-division multiplexing and so forth for improving data transfer efficiency. For example, the data bus of 4n bit width is used as two data bus of 2n bit width in certain period (transfer mode “b”), as one data bus of 4n bit width in a certain period (transfer mode “a”), and further as four data bus of n bit width in a further certain period (transfer mode “c”). A command of switching of the transfer mode is performed by a transfer control circuit common to respective circuit modules. In response to command of the transfer mode, switching of the bit width of data and switching of the bus connecting condition are performed by the bus adapter circuit.

Abstract: A packet receiving circuit 11 splits the packet received from a transmission channel 1 into a fixed length of cells and outputs the cells, a search key extracting circuit 12 extracts a predetermined search key from the above-mentioned cells, a CAM 13 performs retrieval based on the above-mentioned search key and outputs a memory address corresponding to the search key, a matching entry address receiving and associative data address transmitting circuit 14 calculates the memory address of an associative data memory 15 based on the above-mentioned memory address and outputs the information stored in the associative data memory 15 as associative data, a search result (associative data) receiving circuit 16 receives the above-mentioned associative data and performs header updating and destination address of the above-mentioned cells, and a packet transmitting circuit 17 outputs the above-mentioned cells in the form of a packet to a transmission channel 2.

Abstract: An information retrieval system includes two content addressable memories to be searched for m-bit/n-bit codes identical with m-bit/n-bit retrieval key sub-codes, a data memory storing pieces of information relating to different retrieval keys expressed by the combinations of the m-bit/n-bit codes in addressable memory locations assigned addresses, respectively, and an address generating unit supplied with addresses of the m-bit/n-bit codes identical with the m-bit/n-bit retrieval key sub-codes from the content addressable memories so as to generate a target address from the addresses for accessing the piece of information relating to a given retrieval key, whereby the two content addressable memories are searched for the m-bit/n-bit codes substantially in parallel.

Abstract: A memory pool control circuit according to the invention is provided with a CAM (content addressable memory: associative memory) 11. It further has a monitoring module 12, an area unlocking module 13, a local accessing module 14, an area locking module 15, a search control machine 16, and a timer 17. A plurality of tasks (processes) are operating on a processor 18, and one memory 19 is commonly used by the plurality of tasks (processes). When a task (process) has secured a memory space (called a block here), free areas therein are managed by a group of pointers. A block is divided into a plurality of fixed length fields. A group of flags match the memory space (block) in one-to-one correspondence. The flag group indicate whether or not individual fields are being used, i.e. the flag group indicates whether each individual field is being used or unused (free).

Abstract: An integrated circuit has a data transfer system which is simple in switching control and timing extraction of transfer. A bus provided between four modules has a bit width the same as number of bits consisting a transfer data. The bus is divided into a plurality of fractions respectively lying between a plurality of modules. Respective divided fractions are connected by adapters. The adapter includes a lip-flip or the like temporarily holds data to be transmitted from one fraction of the transmission path and outputs to another fraction of the transmission path to form a ring transmission path. Since data flows in a predetermined direction on the bus, control can be simple. Also, since a plurality of modules can perform transmission and reception of data at the same timing, transfer efficiency can be improved significantly.

Abstract: To provide a method of searching a CAM which enables to search an address of matching contents cyclically recorded in a memory array of the CAM with a priority at once, the method of searching a CAM array (2) having first address lines (20), whereof certain are made active when the CAM array (2) is searched with a search key, comprises steps of: obtaining restricted search results by making address lines of the first address lines (20) having addresses lower than a restriction address inactive; selecting logic of third address lines (70) from logic of the restricted search results when any of the restricted search results is active, and from logic of the first address lines (20) as it is, when none of the restricted search results is active; and outputting a searched address by encoding a lowest active address line of the third address lines (70).

Abstract: A transfer control table contains a source memory designation field, a desired region designation field, a shifting amount designation field, and a destination memory designation field. An source selection circuit selects source designation word data from the source word data stored in the source memory according to source memory designation data contained in the source memory designation field to provide the source designation word data. A transfer data bit operation circuit extracts, in response to the source designation word data, only the word data required for transfer as valid word data according to desired region designation data contained in the desired region designation field to shift the valid word data by a bit width that is predetermined based on shifting amount designation data contained in the shifting amount designation field and then to provide the shifted valid word data.

Abstract: An ATM cell sending system includes a first memory, a second memory, a retrieval circuit, and a memory control circuit. The first memory temporarily stores an input cell, outputs a cell storage address, and, in response to input of the cell storage address, outputs the cell stored at the input cell storage address. The second memory stores the cell storage address from the first memory and outputs the readout cell storage address to the first memory. The retrieval circuit uses an address corresponding to a reservation time for cell sending as a start address to retrieve a first free address after the reservation time from the second memory. The memory control circuit writes the cell storage address of the first memory at the free address of the second memory, which is retrieved by the retrieval circuit, and reads out the cell storage address of the first memory from an address of the second memory which corresponds to a current time.

Abstract: A cell interval determination apparatus for usage parameter control, includes a counter, a memory, a cell arrival interval check unit, and a control unit. The counter is incremented every time a cell has arrived in an asynchronous mode to represent a cell arrival time. The memory stores, in units of cell type information, cell information consisting of cell type information included in the cell, the cell arrival time counted by the counter, a cell arrival interval defined value which is set in units of cell type information, and flag information representing a retrieval target/non-retrieval target. The cell arrival interval check unit calculates a time difference between the cell arrival time stored in the memory and the cell arrival time represented by the counter and determines a cell which violates the cell arrival interval defined value stored in the memory.