Patents by Inventor Teruo Katoh

Teruo Katoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9306554
    Abstract: A semiconductor circuit includes an operational amplifier, a voltage drop circuit, and a switch. The operational amplifier has an output terminal connected to an active element that produces a load drive current. A reference voltage is input to the non-inverting input of the operational amplifier. The voltage drop circuit drops a voltage outputted from the operational amplifier. The switch applies a voltage corresponding to a predetermined current flowing when the active element is on to the inverting input of the operational amplifier in a first interval in which the active element is on in response to a predetermined voltage from the operational amplifier. The switch allows the voltage dropped by the voltage drop circuit to be input to the inverting input in a second interval in which the active element is off, thereby shortening a time period until the load drive current starts to flow.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: April 5, 2016
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Teruo Katoh
  • Publication number: 20130278166
    Abstract: A semiconductor circuit includes an operational amplifier, a voltage drop circuit, and a switch. The operational amplifier has an output terminal connected to an active element that produces a load drive current. A reference voltage is input to the non-inverting input of the operational amplifier. The voltage drop circuit drops a voltage outputted from the operational amplifier. The switch applies a voltage corresponding to a predetermined current flowing when the active element is on to the inverting input of the operational amplifier in a first interval in which the active element is on in response to a predetermined voltage from the operational amplifier. The switch allows the voltage dropped by the voltage drop circuit to be input to the inverting input in a second interval in which the active element is off, thereby shortening a time period until the load drive current starts to flow.
    Type: Application
    Filed: April 17, 2013
    Publication date: October 24, 2013
    Applicant: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: TERUO KATOH
  • Patent number: 6940323
    Abstract: A phase locked loop circuit includes a phase comparator, a loop filter, a controlled oscillator, a limiter, a frequency divider, an unlock detecting circuit and a switch. The phase comparator compares an index signal and a reference signal. The loop filter smoothes an output signal of the phase comparator. The controlled oscillator oscillates at a frequency in accordance with an output signal of the loop filter. The limiter connected between an output of the phase comparator and an input of the controlled oscillator. The limiter limits the level of a signal passing therethrough at a predetermined range. The frequency divider divides an output signal of the controlled oscillator and generates the reference signal. The unlock detecting circuit outputs the unlocking of a phase lock based on the index signal and the reference signal. The switch shuts up an output signal of the loop filter based on an unlock detecting signal.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: September 6, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Teruo Katoh, Takaaki Akiyama
  • Publication number: 20040061536
    Abstract: A phase locked loop circuit includes a phase comparator, a loop filter, a controlled oscillator, a limiter, a frequency divider, an unlock detecting circuit and a switch. The phase comparator compares an index signal and a reference signal. The loop filter smoothes an output signal of the phase comparator. The controlled oscillator oscillates at a frequency in accordance with an output signal of the loop filter. The limiter connected between an output of the phase comparator and an input of the controlled oscillator. The limiter limits level of a signal passing therethrough at a predetermined range. The frequency divider divides an output signal of the controlled oscillator and generates the reference signal. The unlock detecting circuit outputs the unlocking of a phase lock based on the index signal and the reference signal. The switch shuts up an output signal of the loop filter based on an unlock detecting signal.
    Type: Application
    Filed: September 26, 2003
    Publication date: April 1, 2004
    Inventors: Teruo Katoh, Takaaki Akiyama
  • Patent number: 6472275
    Abstract: A read-only memory includes a semiconductor substrate; a memory cell matrix which is formed on the semiconductor substrate; and word and bit lines which define the locations of the memory cell matrix. The memory cell matrix includes field effect transistors, each of which turns off when accessed or addressed; and conducting regions, which keep conductive state all the time. Binary data stored in the memory cell matrix are determined by detecting current flowing through the selected bit line.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: October 29, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hiroshi Mizuhashi, Teruo Katoh
  • Publication number: 20010034099
    Abstract: A read-only memory includes a semiconductor substrate; a memory cell matrix which is formed on the semiconductor substrate; and word and bit lines which define the locations of the memory cell matrix. The memory cell matrix includes field effect transistors, each of which turns off when accessed or addressed; and conducting regions, which keep conductive state all the time. Binary data stored in the memory cell matrix are determined by detecting current flowing through the selected bit line.
    Type: Application
    Filed: June 21, 2001
    Publication date: October 25, 2001
    Inventors: Hiroshi Mizuhashi, Teruo Katoh
  • Patent number: 6278629
    Abstract: A read-only memory includes a semiconductor substrate; a memory cell matrix which is formed on the semiconductor substrate; and word and bit lines which define the locations of the memory cell matrix. The memory cell matrix includes field effect transistors, each of which turns off when accessed or addressed; and conducting regions, which keep conductive state all the time. Binary data stored in the memory cell matrix are determined by detecting current flowing through the selected bit line.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: August 21, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hiroshi Mizuhashi, Teruo Katoh
  • Patent number: 5134451
    Abstract: A semiconductive device which comprises a gate insulating film composed of a metal oxide film, source/drain electrodes, and metal silicide layers formed on the source/drain regions is described.
    Type: Grant
    Filed: April 13, 1990
    Date of Patent: July 28, 1992
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Teruo Katoh
  • Patent number: 4814292
    Abstract: In a process of fabricating a semiconductor device, an amorphous semiconductor layer is formed on a substrate, densified by heat-treatment, and is subjected to further heat-treatment to be changed into a polycrystalline semiconductor layer. A MOS transistor can be formed using the polycrystalline semiconductor layer.
    Type: Grant
    Filed: June 19, 1987
    Date of Patent: March 21, 1989
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masayoshi Sasaki, Teruo Katoh