Patents by Inventor Teruo Kurahashi

Teruo Kurahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11936428
    Abstract: An optical device includes an electro-optic crystal layer, a first optical waveguide formed in the electro-optic crystal layer, and an electrode that applies an electric signal to the first optical waveguide. Further, the optical device includes a second optical waveguide in an amorphous state formed in the electro-optic crystal layer and connected to the first optical waveguide.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: March 19, 2024
    Assignee: FUJITSU OPTICAL COMPONENTS LIMITED
    Inventors: Shuntaro Makino, Teruo Kurahashi
  • Patent number: 11693290
    Abstract: An optical waveguide device includes a substrate on which an intermediate layer, a thin-film LN layer of lithium niobate, and a buffer layer are stacked; an optical waveguide formed in the thin-film LN layer; and a plurality of electrodes near the optical waveguide. The intermediate layer and the buffer layer contain a same material of a metal element of any one of group 3 of group 18 of a periodic table of elements.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: July 4, 2023
    Assignee: Fujitsu Optical Components Limited
    Inventors: Shuntaro Makino, Yoshinobu Kubota, Yasuhiro Ohmori, Masaharu Doi, Teruo Kurahashi, Shintaro Takeuchi
  • Publication number: 20230161184
    Abstract: An optical device includes a substrate, a first cladding layer that is laminated on one surface of the substrate, and a first optical waveguide that is formed in the first cladding layer at a side opposite to the substrate in the first cladding layer. The optical device further includes an electro-optic crystal layer that is laminated on a surface of the first cladding layer at a side opposite to the substrate, and a second optical waveguide that is formed of the electro-optic crystal layer on a surface of the electro-optic crystal layer at a side opposite to the first cladding layer. The optical device further includes a second cladding layer that is laminated on a surface of the electro-optic crystal layer at a side opposite to the first cladding layer.
    Type: Application
    Filed: September 19, 2022
    Publication date: May 25, 2023
    Applicant: FUJITSU OPTICAL COMPONENTS LIMITED
    Inventors: Shuntaro MAKINO, Teruo KURAHASHI, Yoshinobu KUBOTA, Yoshihiko YOSHIDA, Nobuaki MITAMURA, Takehito TANAKA
  • Publication number: 20230141163
    Abstract: An optical device includes an electro-optic crystal layer, a first optical waveguide formed in the electro-optic crystal layer, and an electrode that applies an electric signal to the first optical waveguide. Further, the optical device includes a second optical waveguide in an amorphous state formed in the electro-optic crystal layer and connected to the first optical waveguide.
    Type: Application
    Filed: September 16, 2022
    Publication date: May 11, 2023
    Applicant: Fujitsu Optical Components Limited
    Inventors: Shuntaro Makino, Teruo Kurahashi
  • Patent number: 11624965
    Abstract: An optical waveguide device includes an intermediate layer, a thin-film LN layer including X-cut lithium niobate, and a buffer layer stacked on a substrate; an optical waveguide formed in the thin-film LN layer; and an electrode for driving. The intermediate layer is formed by an upper first intermediate layer and a lower second intermediate layer, the second intermediate layer having a permittivity that is smaller than a permittivity of the first intermediate layer.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: April 11, 2023
    Assignee: FUJITSU OPTICAL COMPONENTS LIMITED
    Inventors: Shuntaro Makino, Yoshinobu Kubota, Yasuhiro Ohmori, Masaharu Doi, Teruo Kurahashi
  • Publication number: 20230004028
    Abstract: An optical device includes a thin film Lithium Niobate (LN) layer, a first optical waveguide, and a second optical waveguide. The thin film LN layer is an X-cut or a Y-cut LN layer. The first optical waveguide is an optical waveguide that is formed on the thin film LN layer along a direction that is substantially perpendicular to a Z direction of a crystal axis of the thin film LN layer. The second optical waveguide is an optical waveguide that is routed and connected to the first optical waveguide. At least a part of a core of the first optical waveguide is made thicker than a core of the second optical waveguide.
    Type: Application
    Filed: April 21, 2022
    Publication date: January 5, 2023
    Applicant: FUJITSU OPTICAL COMPONENTS LIMITED
    Inventors: Shuntaro MAKINO, Yoshinobu KUBOTA, Yasuhiro OHMORI, Masaharu DOI, Masaki SUGIYAMA, Shintaro TAKEUCHI, Yoshihiko YOSHIDA, Shinji MARUYAMA, Teruo KURAHASHI
  • Publication number: 20220050351
    Abstract: An optical waveguide device includes an intermediate layer, a thin-film LN layer including X-cut lithium niobate, and a buffer layer stacked on a substrate; an optical waveguide formed in the thin-film LN layer; and an electrode for driving. The intermediate layer is formed by an upper first intermediate layer and a lower second intermediate layer, the second intermediate layer having a permittivity that is smaller than a permittivity of the first intermediate layer.
    Type: Application
    Filed: June 17, 2021
    Publication date: February 17, 2022
    Applicant: Fujitsu Optical Components Limited
    Inventors: Shuntaro Makino, Yoshinobu Kubota, Yasuhiro Ohmori, Masaharu Doi, Teruo Kurahashi
  • Publication number: 20210325760
    Abstract: An optical waveguide device includes a substrate on which an intermediate layer, a thin-film LN layer of lithium niobate, and a buffer layer are stacked; an optical waveguide formed in the thin-film LN layer; and a plurality of electrodes near the optical waveguide. The intermediate layer and the buffer layer contain a same material of a metal element of any one of group 3 of group 18 of a periodic table of elements.
    Type: Application
    Filed: February 2, 2021
    Publication date: October 21, 2021
    Applicant: Fujitsu Optical Components Limited
    Inventors: Shuntaro Makino, Yoshinobu Kubota, Yasuhiro Ohmori, Masaharu Doi, Teruo Kurahashi, Shintaro Takeuchi
  • Publication number: 20190181616
    Abstract: An optical device includes lower cladding layer formed of an amorphous insulator on a substrate; a first cladding region, an active region, and a second cladding region formed on the lower cladding layer, one of the first cladding region and the second cladding region being formed on a monocrystal; an upper cladding layer formed of an insulator on the active region; a first electrode connected with the first cladding region; and a second electrode connected with the second cladding region.
    Type: Application
    Filed: February 18, 2019
    Publication date: June 13, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Teruo Kurahashi, Kenichi Kawaguchi
  • Patent number: 8470653
    Abstract: A method for manufacturing a P-type MOS transistor includes forming a gate insulating film on the substrate, forming a gate electrode from amorphous silicon containing no impurities on the gate insulating film, performing a heat treatment for controlling the film characteristics of the amorphous silicon, depositing a nickel (Ni) layer on the gate electrode, and forming nickel silicides from the gate electrode and the nickel (Ni).
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: June 25, 2013
    Assignee: Fujitsu Limited
    Inventors: Teruo Kurahashi, Yasuyoshi Mishima, Yukie Sakita
  • Patent number: 7968466
    Abstract: A method for fabricating an electron device on a substrate includes the steps of forming a dummy film over the substrate such that the dummy film covers a device region of the substrate and an outer region of the substrate outside the device region, forming a dummy pattern by patterning the dummy film such that the dummy pattern has a first height in the device region and a second height smaller than the first height in the outer region, forming another film over the substrate such that the film covers the dummy pattern in the device region and in the outer region with a shape conformal to a cross-sectional shape of the dummy pattern, and applying an anisotropic etching process acting generally perpendicularly to the substrate such that a surface of the substrate is exposed in the device region and in the outer region.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: June 28, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kenji Ishikawa, Hideharu Shido, Takeo Nagata, Teruo Kurahashi, Yasuyoshi Mishima
  • Patent number: 7947547
    Abstract: A semiconductor device fabrication method by which CMOS transistors with low-resistance metal gate electrodes each having a proper work function can be fabricated. A HfN layer in which nitrogen concentration in an nMOS transistor formation region differs from nitrogen concentration in a pMOS transistor formation region is formed. A MoN layer is formed over the HfN layer and heat treatment is performed. Nitrogen diffuses from the MoN layer into the HfN layer in which nitrogen concentration is low and a work function is set by the HfN layer according to nitrogen concentration which depends on the nitrogen content of the HfN layer before the heat treatment and the amount of nitrogen that diffuses into the HfN layer. On the other hand, nitrogen hardly diffuses from the MoN layer into the HfN layer which originally has a certain nitrogen content, and a work function is set by the HfN layer according to nitrogen concentration in the HfN layer before the heat treatment.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: May 24, 2011
    Assignee: Fujitsu Limited
    Inventors: Teruo Kurahashi, Manabu Sakamoto, Yasuyoshi Mishima
  • Publication number: 20100044799
    Abstract: A method for manufacturing a P-type MOS transistor includes forming a gate insulating film on the substrate, forming a gate electrode from amorphous silicon containing no impurities on the gate insulating film, performing a heat treatment for controlling the film characteristics of the amorphous silicon, depositing a nickel (Ni) layer on the gate electrode, and forming nickel silicides from the gate electrode and the nickel (Ni).
    Type: Application
    Filed: August 14, 2009
    Publication date: February 25, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Teruo Kurahashi, Yasuyoshi Mishima, Yukie Sakita
  • Patent number: 7612400
    Abstract: An MIM device includes a lower electrode of a metal nitride film, a hysteresis film of an oxide film containing Nb formed on the lower electrode, and an upper electrode of a metal nitride film formed on the hysteresis film.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: November 3, 2009
    Assignee: Fujitsu Limited
    Inventors: Teruo Kurahashi, Hideharu Shido, Kenji Ishikawa, Takeo Nagata, Yasuyoshi Mishima, Yukie Sakita
  • Publication number: 20080242068
    Abstract: A semiconductor device fabrication method by which CMOS transistors with low-resistance metal gate electrodes each having a proper work function can be fabricated. A HfN layer in which nitrogen concentration in an nMOS transistor formation region differs from nitrogen concentration in a pMOS transistor formation region is formed. A MoN layer is formed over the HfN layer and heat treatment is performed. Nitrogen diffuses from the MoN layer into the HfN layer in which nitrogen concentration is low and a work function is set by the HfN layer according to nitrogen concentration which depends on the nitrogen content of the HfN layer before the heat treatment and the amount of nitrogen that diffuses into the HfN layer. On the other hand, nitrogen hardly diffuses from the MoN layer into the HfN layer which originally has a certain nitrogen content, and a work function is set by the HfN layer according to nitrogen concentration in the HfN layer before the heat treatment.
    Type: Application
    Filed: June 12, 2008
    Publication date: October 2, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Teruo KURAHASHI, Manabu SAKAMOTO, Yasuyoshi MISHIMA
  • Publication number: 20080121858
    Abstract: An MIM device includes a lower electrode of a metal nitride film, a hysteresis film of an oxide film containing Nb formed on the lower electrode, and an upper electrode of a metal nitride film formed on the hysteresis film.
    Type: Application
    Filed: November 26, 2007
    Publication date: May 29, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Teruo KURAHASHI, Hideharu SHIDO, Kenji ISHIKAWA, Takeo NAGATA, Yasuyoshi MISHIMA, Yukie SAKITA
  • Publication number: 20080124933
    Abstract: A method for fabricating an electron device on a substrate includes the steps of forming a dummy film over the substrate such that the dummy film covers a device region of the substrate and an outer region of the substrate outside the device region, forming a dummy pattern by patterning the dummy film such that the dummy patter has a first height in the device region and a second height smaller than the first height in the outer region, forming another film over the substrate such that the film covers the dummy pattern in the device region and in the outer region with a shape conformal to a cross-sectional shape of the dummy pattern, and applying an anisotropic etching process acting generally perpendicularly to the substrate such that a surface of the substrate is exposed in the device region and in the outer region.
    Type: Application
    Filed: November 27, 2007
    Publication date: May 29, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Kenji Ishikawa, Hideharu Shido, Takeo Nagata, Teruo Kurahashi, Yasuyoshi Mishima
  • Publication number: 20060208318
    Abstract: A high-performance CMOS field effect semiconductor device using metal gate electrodes. An n-type gate electrode and a p-type gate electrode are formed by using a same metal and differ in nitrogen concentration. As a result, a high-performance CMOS field effect semiconductor device having the n-type gate electrode and the p-type gate electrode between which a work function difference is a predetermined value can be realized. By forming a low-resistance layer on layers which are formed by using the same metal and which differ in nitrogen concentration, it is possible to reduce the resistance of the n-type gate electrode and the p-type gate electrode while controlling the work functions of the n-type gate electrode and the p-type gate electrode. Therefore, a higher-performance CMOS field effect semiconductor device can be realized.
    Type: Application
    Filed: March 9, 2006
    Publication date: September 21, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Manabu Sakamoto, Teruo Kurahashi, Yasuyoshi Mishima
  • Patent number: 5680497
    Abstract: This invention aims at providing an optical waveguide device capable of stably operating for an extended period of time. The optical waveguide device comprises an optical waveguide path formed inside a surface of an electro-optical substrate, a buffer layer formed on the optical waveguide path, and a driving electrode for impressing an electric field so as to change a refractive index of the optical waveguide path, wherein the buffer layer is made of a transparent dielectric or insulator of a mixture between silicon dioxide and an oxide of at least one element selected from the group consisting of the metal elements of the Groups III to VIII, Ib and IIb of the Periodic Table and semiconductor elements other than silicon, or a transparent dielectric or insulator of an oxide between silicon and at least one of the metal elements and semiconductor elements described above.
    Type: Grant
    Filed: December 7, 1994
    Date of Patent: October 21, 1997
    Assignee: Fujitsu Limited
    Inventors: Minoru Seino, Tadao Nakazawa, Takashi Yamane, Yoshinobu Kubota, Masaharu Doi, Kunio Sugeta, Teruo Kurahashi
  • Patent number: 5404412
    Abstract: This invention aims at providing an optical waveguide device capable of stably operating for an extended period of time. The optical waveguide device comprises an optical waveguide path formed inside a surface of an electro-optical substrate, a buffer layer formed on the optical waveguide path, and a driving electrode for impressing an electric field so as to change a refractive index of the optical waveguide path, wherein the buffer layer is made of a transparent dielectric or insulator of a mixture between silicon dioxide and an oxide of at least one element selected from the group consisting of the metal elements of the Groups III to VIII, Ib and IIb of the Periodic Table and semiconductor elements other than silicon, or a transparent dielectric or insulator of an oxide between silicon and at least one of the metal elements and semiconductor elements described above.
    Type: Grant
    Filed: December 24, 1992
    Date of Patent: April 4, 1995
    Assignee: Fujitsu Limited
    Inventors: Minoru Seino, Tadao Nakazawa, Takashi Yamane, Yoshinobu Kubota, Masaharu Doi, Kunio Sugeta, Teruo Kurahashi