Patents by Inventor Teruo Murase
Teruo Murase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6539137Abstract: A signal coupler is comprised of a transmitting section and a receiving section. The receiving section includes a polymer pyroelectric film element having a greater than 1% by volume of a high thermal diffusivity material, such as aluminum nitride, to improve the thermal diffusivity of the polymer film. A preferred embodiment of the transmitting section includes a thin film resistive heater to generate thermal pulses which are coupled to the receiving section by a thin film of thermal grease disposed between the receiving section and the transmitting section.Type: GrantFiled: March 8, 2000Date of Patent: March 25, 2003Assignee: Fujitsu LimitedInventors: Larry L. Moresco, Vivek Mansingh, Teruo Murase
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Patent number: 6102710Abstract: An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed through rigid segments and signals are routed through a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected.Type: GrantFiled: April 30, 1998Date of Patent: August 15, 2000Assignee: Fujitsu LimitedInventors: Solomon I. Beilin, William T. Chou, David Kudzuma, Michael G. Lee, Michael G. Peters, James J. Roman, Som S. Swamy, Wen-chou Vincent Wang, Larry L. Moresco, Teruo Murase
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Patent number: 5854534Abstract: An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed though rigid segments and signals are routed though a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected.Type: GrantFiled: November 16, 1995Date of Patent: December 29, 1998Assignee: Fujitsu LimitedInventors: Solomon I. Beilin, William T. Chou, David Kudzuma, Michael G. Lee, Michael G. Peters, James J. Roman, Som S. Swamy, Wen-chou Vincent Wang, Larry L. Moresco, Teruo Murase
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Patent number: 5778529Abstract: A multichip module substrate for use in a three-dimensional multichip module, and methods of making the same, are disclosed. The substrate comprises a thin film structure, for routing signals to and from integrated circuit chips, formed over a rigid support base. Apertures are formed in the support base exposing the underside of the thin film structure, thereby allowing high density connectors to be mounted on both surfaces of the thin film structure, greatly enhancing the ability to communicate signals between adjacent substrates in the chip module. This avoids the need to route the signals either through the rigid support base or to the edges of the thin film structure. Power and ground, which do not require a high connection density, are routed in low impedance paths through the support base. Preferably, the thin film structure is made of alternating layers of patterned metal, such as copper, and a low dielectric organic polymer, such as a polyimide.Type: GrantFiled: May 22, 1996Date of Patent: July 14, 1998Assignee: Fujitsu LimitedInventors: Solomon I. Beilin, William T. Chou, David Kudzuma, Michael G. Lee, Teruo Murase, Michael G. Peters, James J. Roman, Som S. Swamy, Wen-Chou Vincent Wang
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Patent number: 5544017Abstract: A multichip module substrate for use in a three-dimensional multichip module, and methods of making the same, are disclosed. The substrate comprises a thin film structure, for routing signals to and from integrated circuit chips, formed over a rigid support base. Apertures are formed in the support base exposing the underside of the thin film structure, thereby allowing high density connectors to be mounted on both surfaces of the thin film structure, greatly enhancing the ability to communicate signals between adjacent substrates in the chip module. This avoids the need to route the signals either through the rigid support base or to the edges of the thin film structure. Power and ground, which do not require a high connection density, are routed in low impedance paths through the support base. Preferably, the thin film structure is made of alternating layers of patterned metal, such as copper, and a low dielectric organic polymer, such as a polyimide.Type: GrantFiled: July 19, 1994Date of Patent: August 6, 1996Assignee: Fujitsu LimitedInventors: Solomon I. Beilin, William T. Chou, David Kudzuma, Michael G. Lee, Teruo Murase, Michael G. Peters, James J. Roman, Som S. Swamy, Wen-chou V. Wang
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Patent number: 5181317Abstract: A method of making an engineering change to a printed wiring board changes connection for a terminal of an electronic component which is mounted on the printed wiring board through a terminal pad. The terminal is electrically connected to a destination through the terminal pad and wiring within the printed wiring board. The present invention places an insulator, including an insulating material and a conductive layer formed thereon, between the terminal and the terminal pad. The electronic component is mounted on the printed wiring board and the terminal is electrically connected to the conductive layer. A discrete wire is placed between the conductive layer and the destination.Type: GrantFiled: September 27, 1991Date of Patent: January 26, 1993Assignee: Fujitsu LimitedInventors: Mikio Nishihara, Teruo Murase, Kiyotaka Seyama, Kiyoshi Kuwabara, Osamu Ohshima
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Patent number: 5017738Abstract: A connecting apparatus wherein a porous silver plating layers are provided on surface pads of a printed circuit board and on a surface of a contact provided on the pads of a mother board. The plating layers are respectively impregnated with tin-zinc alloy and gallium. The electrical connection is established between the pads of the printed circuit board and the pads of the mother board through a liquid alloy by placing the plating layers in contact with each other. For the first printed circuit board having the pads and spacer, the gallium particles are adhered to the pads, while solder is temporarily adhered to the spacer. For the second printed circuit board having the pads and the connecting pads, tin or indium layer is provided on the surface of the pads, then the spacer of the first printed circuit board is positioned and fixed to the connecting pad of the second printed circuit board.Type: GrantFiled: February 22, 1990Date of Patent: May 21, 1991Assignee: Fujitsu LimitedInventors: Hiroki Tsuji, Kyoichiro Kawano, Teruo Murase
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Patent number: 4998884Abstract: An apparatus for connecting a high density cable assembly having a shield and to be connected to corresponding contact pins provided on a substrate having a grounding grid formed of conductive guides, each having a predetermined number of contact pins therein, including a connector to which the cable assembly is connected and which is to be mounted to the associated guide. The connector has a connector body, a connector cover surrounding the connector body, and a latching device provided between the connector cover and the connector body for easily latching and unlatching the connector to and from the associated guides.Type: GrantFiled: January 26, 1989Date of Patent: March 12, 1991Assignees: Fujitsu Limited, Amdahl CorporationInventors: Kouji Ishikawa, Kyoichiro Kawano, Teruo Murase, Jerzy R. Sochor, C. Timothy Norman
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Patent number: 4815987Abstract: An electrical connector includes a plug having a number of contact pins and a jack having a number of receptacle contacts corresponding to the contact pins. Each of the receptacle contacts has a parallel portion and a widened portion. A contact pressing member having partition walls is movable in such a manner that, when the contact pressing member is in a first position, the partition walls are positioned at the parallel portions of the receptacle contacts to allow an easy insertion of the contact pins. When the contact pressing member is moved to a second position, the partition walls are moved to the widened portions of the receptacle contacts so that the gaps between the widened portions are narrowed. Therefore, the receptacle contacts are pressed into firm contact with the contact pins.Type: GrantFiled: December 22, 1987Date of Patent: March 28, 1989Assignee: Fujitsu LimitedInventors: Kyoichiro Kawano, Hiroki Tsuji, Teruo Murase
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Patent number: 4352533Abstract: A connector device for printed boards, comprising at least one pair of opposed male connectors on the printed boards, each male connector having at least one projecting terminal, at least one female connector which is movably attached to the terminals of one of the male connectors. The electrical connection between the corresponding projecting terminals of the two opposing male connectors being established and broken by the displacement of the female connectors.Type: GrantFiled: June 18, 1980Date of Patent: October 5, 1982Assignee: Fujitsu LimitedInventors: Teruo Murase, Kyoichiro Kawano, Akiyoshi Oshitani
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Patent number: 4237606Abstract: In a method of manufacture of a multilayer ceramic board, a conductor land is formed and baked on a first substrate. A second substrate on which the wiring pattern is formed is then electrically connected to the first substrate via the land. An error in the substrate due to shrinkage at the time of sintering is thereby compensated by the conductor land. This assures the formation of a highly accurate wiring pattern on the sintered substrate surface, despite shrinkage of the ceramic during sintering of the raw sheets of ceramic.Type: GrantFiled: August 11, 1978Date of Patent: December 9, 1980Assignee: Fujitsu LimitedInventors: Koichi Niwa, Teruo Murase, Masatoshi Fujimori, Kyohei Murakawa