Patents by Inventor Teruo Ono
Teruo Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230282262Abstract: The present invention provides a layer structure for a magnetic memory element in which the drive current required for domain wall motion is reduced, and the controllability of domain wall motion is improved, and provides a magnetic memory element having the layer structure. A layer structure (9) for a magnetic memory element (10) comprises multiple first ferromagnetic layers (1) with a switchable spin state and boundary layers (2) each located between each pair of the multiple first ferromagnetic layers (1) to form a domain wall, the boundary layers (2) being for generating ferromagnetic interaction (Aex) between the multiple first ferromagnetic layers (1).Type: ApplicationFiled: July 12, 2021Publication date: September 7, 2023Inventor: Teruo ONO
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Patent number: 11302373Abstract: A race track magnetic memory device includes a magnetic fine wire having a plurality of magnetic domains, a magnetic tunnel junction element comprising a pinned layer and an insulating layer, and a spin-orbit torque (SOT) generator. An easy axis of the magnetic fine wire is substantially perpendicular to a contact surface of the magnetic fine wire and the SOT generator. The magnetic tunnel junction element and the SOT generator are disposed on a magnetic domain write region of the magnetic fine wire. Data is written by generating spin-transfer torque at magnetization of the magnetic domain write region by flowing a first current in the magnetic tunnel junction element and by generating spin-orbit torque at the magnetization of the magnetic domain write region by flowing a second current in the SOT generator.Type: GrantFiled: October 21, 2020Date of Patent: April 12, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Yoshiaki Sonobe, Syuta Honda, Teruo Ono
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Publication number: 20210125653Abstract: A race track magnetic memory device includes a magnetic fine wire having a plurality of magnetic domains, a magnetic tunnel junction element comprising a pinned layer and an insulating layer, and a spin-orbit torque (SOT) generator. An easy axis of the magnetic fine wire is substantially perpendicular to a contact surface of the magnetic fine wire and the SOT generator. The magnetic tunnel junction element and the SOT generator are disposed on a magnetic domain write region of the magnetic fine wire. Data is written by generating spin-transfer torque at magnetization of the magnetic domain write region by flowing a first current in the magnetic tunnel junction element and by generating spin-orbit torque at the magnetization of the magnetic domain write region by flowing a second current in the SOT generator.Type: ApplicationFiled: October 21, 2020Publication date: April 29, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Yoshiaki SONOBE, Syuta HONDA, Teruo ONO
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Patent number: 8345473Abstract: The present invention uses a ferromagnetic thin wire having a domain wall inside, with the magnetic moment at the center thereof being perpendicular to the longitudinal axis of the thin wire. With the domain wall being fixed by a domain wall fixation device (e.g. antiferromagnetic thin wires) so that the domain wall is prevented from moving in the ferromagnetic thin wire, when a direct current is supplied, the magnetic moment rotates in the immobilized domain wall. This rotation of the moment can be detected by a TMR element or the like. This configuration of the ferromagnetic thin wire element can be directly used to create a microwave oscillator or magnetic memory.Type: GrantFiled: April 21, 2008Date of Patent: January 1, 2013Assignees: Kyoto University, University of Electro-CommunicationsInventors: Teruo Ono, Yoshinobu Nakatani
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Patent number: 7952915Abstract: A novel element capable of simply controlling an in-plane rotational motion of a core (a rising spot of a magnetization) generated in the center of a ferromagnetic dot made by forming a ferromagnetic material into a nanosized disk shape is provided. In addition, a binary information memory element using a core, including a ferromagnetic dot, made of a disk-shaped ferromagnetic material, with a magnetic structure of a magnetic vortex structure, and a current supplier for supplying an alternating current with a predetermined alternating current in the radial direction of the ferromagnetic dot is provided. In the case where the frequency of the current resonates with the intrinsic frequency of the ferromagnetic dot, it is possible to rotate the core in the plane of the dot. Since the core leaks a magnetic field, a microscopic actuator such as a motor can be obtained by using this element. Furthermore, supplying a current having a density not less than a predetermined value reverses the core.Type: GrantFiled: March 1, 2007Date of Patent: May 31, 2011Assignees: Kyoto University, The University of Electro-Communications, Osaka University, Tokyo Metropolitan UniversityInventors: Teruo Ono, Shinya Kasai, Kensuke Kobayashi, Yoshinobu Nakatani, Hiroshi Kohno, Gen Tatara
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Publication number: 20110069541Abstract: The present invention uses a ferromagnetic thin wire having a domain wall inside, with the magnetic moment at the center thereof being perpendicular to the longitudinal axis of the thin wire. With the domain wall being fixed by a domain wall fixation device (e.g. antiferromagnetic thin wires) so that the domain wall is prevented from moving in the ferromagnetic thin wire, when a direct current is supplied, the magnetic moment rotates in the immobilized domain wall. This rotation of the moment can be detected by a TMR element or the like. This configuration of the ferromagnetic thin wire element can be directly used to create a microwave oscillator or magnetic memory.Type: ApplicationFiled: April 21, 2008Publication date: March 24, 2011Applicants: KYOTO UNIVERSITY, THE UNIVERSITY OF ELECTRO-COMMUNICATIONSInventors: Teruo Ono, Yoshinobu Nakatani
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Publication number: 20100215851Abstract: A method of producing core/shell composite nano-particles exhibiting superior characteristics, by using as cores nano-particles heat treated in advance so as to give them a specific crystal structure in a state using a barrier layer to prevent sintering and forming shells on their surface, which eliminates hindrances to the shell forming reaction due to the phase transfer catalyst or other strongly sticky dispersant, is provided.Type: ApplicationFiled: April 25, 2007Publication date: August 26, 2010Inventors: Tetsuya Shoji, Naoki Nakamura, Akira Kato, Shinpei Yamamoto, Mikio Takano, Teruo Ono
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Publication number: 20100157662Abstract: In one embodiment of the present invention, an MRAM is an MRAM including: a plurality of write word lines; a plurality of bit lines provided so as to intersect with the write word lines; and TMR elements provided at respective intersections of the write word lines and the bit lines. Each of the TMR elements includes a first ferromagnetic layer of which magnetization direction is variable, a second ferromagnetic layer of which magnetization direction is fixed, and a tunnel wall which is sandwiched between the first ferromagnetic layer and the second ferromagnetic layer. The bit line is provided, for example, so as to bulge in the direction in which the write word line extends at the intersection of the bit line and the write word line, so that a magnetic wall is introduced at a desired position of the bit line. Further, a current fed through the bit line is fed through the first ferromagnetic layer at the time of data writing. This makes it possible to provide the MRAM having a gigabit-class capacity.Type: ApplicationFiled: April 26, 2006Publication date: June 24, 2010Inventors: Teruo Ono, Akinobu Yamaguchi, Saburo Nasu
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Publication number: 20090180311Abstract: The present invention provides a novel element capable of simply controlling an in-plane rotational motion of a core (a rising spot of a magnetization) generated in the center of a ferromagnetic dot made by forming a ferromagnetic material into a nanosized disk shape. In addition, the present invention is achieved to provide a binary information memory element using a core, including a ferromagnetic dot, made of a disk-shaped ferromagnetic material, with a magnetic structure of a magnetic vortex structure, and a current supplier for supplying an alternating current with a predetermined alternating current in the radial direction of the ferromagnetic dot. In the case where the frequency of the current resonates with the intrinsic frequency of the ferromagnetic dot, it is possible to rotate the core in the plane of the dot. Since the core leaks a magnetic field, a microscopic actuator such as a motor can be obtained by using this element.Type: ApplicationFiled: March 1, 2007Publication date: July 16, 2009Applicants: Kyoto University, The University of Electro-Communications, Osaka University, Tokyo Metropolitan UniversityInventors: Teruo Ono, Shinya Kasai, Kensuke Kobayashi, Yoshinobu Nakatani, Hiroshi Kohno, Gen Tatara
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Publication number: 20070259133Abstract: A FePt alloy nanoparticle, which is expected to be a promising material used for an ultra-high-density magnetic recording medium of the next generation, is ordered by heat treatment to have high magnetic anisotropy, but there has been a problem that the particles are coalesced with each other and agglomerate during the heat treatment. According to the present invention, each particle of the alloy nanoparticles is covered with a coating such as SiO2, and thereafter a heat treatment for ordering is carried out. In this method, the alloy nanoparticles do not coalesce with each other even if the heat treatment is performed at such a high temperature as to allow all the particles to be fully ordered. After the heat treatment, only the coating is removed using an acid or alkali solution so that it is possible to obtain ordered alloy phase nanoparticles which are ordered and dispersible in various solutions.Type: ApplicationFiled: December 7, 2005Publication date: November 8, 2007Applicant: KYOTO UNIVERSITYInventors: Teruo Ono, Shinpei Yamamoto, Yasumasa Morimoto, Mikio Takano
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Patent number: 6555763Abstract: A multilayered circuit board for a semiconductor chip module includes an underlying board, insulating layers, fixed-potential wiring layers, via holes, and metal layers. The underlying board has a major surface made of a metal material to which a fixed potential is applied. The insulating layers are stacked on the major surface of the underlying board and have wiring layers formed on their surfaces. The fixed-potential wiring layers constitute part of the wiring layers formed on the insulating layers. The via holes are formed below the fixed-potential wiring layers to extend through the insulating layers. The metal layers are filled in the via holes so as to make upper ends be connected to the lower surfaces of the fixed-potential wiring layers. One of the insulating layers in contact with the major surface of the underlying board is formed on the underlying board while the lower end of the metal layer is in contact with the major surface of the underlying board.Type: GrantFiled: September 15, 1999Date of Patent: April 29, 2003Assignees: Fuchigami Micro Co., Ltd., NEC Compound Semiconductor Devices Ltd.Inventors: Koki Hirasawa, Teruo Ono
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Patent number: 6351026Abstract: A multilayered wiring structure includes a lower wiring layer, an interlevel insulating layer, a filling layer, an upper wiring layer, and a plated layer. The lower wiring layer is formed on a lead frame through an insulating layer. The interlevel insulating layer is formed on the lower wiring layer to have a via hole at a predetermined region thereof to expose an upper portion of the lower wiring layer. The filling layer is made of a conductive material to fill the via hole. The upper wiring layer is formed on the interlevel insulating layer to have an opening above a portion where the via hole is formed. The plated layer is formed on the upper wiring layer to be connected to the filling layer. A method of manufacturing a multilayered wiring structure is also disclosed.Type: GrantFiled: June 27, 2001Date of Patent: February 26, 2002Assignee: NEC CorporationInventors: Koki Hirasawa, Teruo Ono
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Publication number: 20010038149Abstract: A multilayered wiring structure includes a lower wiring layer, an interlevel insulating layer, a filling layer, an upper wiring layer, and a plated layer. The lower wiring layer is formed on a lead frame through an insulating layer. The interlevel insulating layer is formed on the lower wiring layer to have a via hole at a predetermined region thereof to expose an upper portion of the lower wiring layer. The filling layer is made of a conductive material to fill the via hole. The upper wiring layer is formed on the interlevel insulating layer to have an opening above a portion where the via hole is formed. The plated layer is formed on the upper wiring layer to be connected to the filling layer. A method of manufacturing a multilayered wiring structure is also disclosed.Type: ApplicationFiled: June 27, 2001Publication date: November 8, 2001Inventors: Koki Hirasawa, Teruo Ono
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Patent number: 6274404Abstract: A multilayered wiring structure includes a lower wiring layer, an interlevel insulating layer, a filling layer, an upper wiring layer, and a plated layer. The lower wiring layer is formed on a lead frame through an insulating layer. The interlevel insulating layer is formed on the lower wiring layer to have a via hole at a predetermined region thereof to expose an upper portion of the lower wiring layer. The filling layer is made of a conductive material to fill the via hole. The upper wiring layer is formed on the interlevel insulating layer to have an opening above a portion where the via hole is formed. The plated layer is formed on the upper wiring layer to be connected to the filling layer. A method of manufacturing a multilayered wiring structure is also disclosed.Type: GrantFiled: September 22, 1999Date of Patent: August 14, 2001Assignee: NEC CorporationInventors: Koki Hirasawa, Teruo Ono