Patents by Inventor Teruo Ono

Teruo Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230282262
    Abstract: The present invention provides a layer structure for a magnetic memory element in which the drive current required for domain wall motion is reduced, and the controllability of domain wall motion is improved, and provides a magnetic memory element having the layer structure. A layer structure (9) for a magnetic memory element (10) comprises multiple first ferromagnetic layers (1) with a switchable spin state and boundary layers (2) each located between each pair of the multiple first ferromagnetic layers (1) to form a domain wall, the boundary layers (2) being for generating ferromagnetic interaction (Aex) between the multiple first ferromagnetic layers (1).
    Type: Application
    Filed: July 12, 2021
    Publication date: September 7, 2023
    Inventor: Teruo ONO
  • Patent number: 11302373
    Abstract: A race track magnetic memory device includes a magnetic fine wire having a plurality of magnetic domains, a magnetic tunnel junction element comprising a pinned layer and an insulating layer, and a spin-orbit torque (SOT) generator. An easy axis of the magnetic fine wire is substantially perpendicular to a contact surface of the magnetic fine wire and the SOT generator. The magnetic tunnel junction element and the SOT generator are disposed on a magnetic domain write region of the magnetic fine wire. Data is written by generating spin-transfer torque at magnetization of the magnetic domain write region by flowing a first current in the magnetic tunnel junction element and by generating spin-orbit torque at the magnetization of the magnetic domain write region by flowing a second current in the SOT generator.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: April 12, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoshiaki Sonobe, Syuta Honda, Teruo Ono
  • Publication number: 20210125653
    Abstract: A race track magnetic memory device includes a magnetic fine wire having a plurality of magnetic domains, a magnetic tunnel junction element comprising a pinned layer and an insulating layer, and a spin-orbit torque (SOT) generator. An easy axis of the magnetic fine wire is substantially perpendicular to a contact surface of the magnetic fine wire and the SOT generator. The magnetic tunnel junction element and the SOT generator are disposed on a magnetic domain write region of the magnetic fine wire. Data is written by generating spin-transfer torque at magnetization of the magnetic domain write region by flowing a first current in the magnetic tunnel junction element and by generating spin-orbit torque at the magnetization of the magnetic domain write region by flowing a second current in the SOT generator.
    Type: Application
    Filed: October 21, 2020
    Publication date: April 29, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yoshiaki SONOBE, Syuta HONDA, Teruo ONO
  • Patent number: 8345473
    Abstract: The present invention uses a ferromagnetic thin wire having a domain wall inside, with the magnetic moment at the center thereof being perpendicular to the longitudinal axis of the thin wire. With the domain wall being fixed by a domain wall fixation device (e.g. antiferromagnetic thin wires) so that the domain wall is prevented from moving in the ferromagnetic thin wire, when a direct current is supplied, the magnetic moment rotates in the immobilized domain wall. This rotation of the moment can be detected by a TMR element or the like. This configuration of the ferromagnetic thin wire element can be directly used to create a microwave oscillator or magnetic memory.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: January 1, 2013
    Assignees: Kyoto University, University of Electro-Communications
    Inventors: Teruo Ono, Yoshinobu Nakatani
  • Patent number: 7952915
    Abstract: A novel element capable of simply controlling an in-plane rotational motion of a core (a rising spot of a magnetization) generated in the center of a ferromagnetic dot made by forming a ferromagnetic material into a nanosized disk shape is provided. In addition, a binary information memory element using a core, including a ferromagnetic dot, made of a disk-shaped ferromagnetic material, with a magnetic structure of a magnetic vortex structure, and a current supplier for supplying an alternating current with a predetermined alternating current in the radial direction of the ferromagnetic dot is provided. In the case where the frequency of the current resonates with the intrinsic frequency of the ferromagnetic dot, it is possible to rotate the core in the plane of the dot. Since the core leaks a magnetic field, a microscopic actuator such as a motor can be obtained by using this element. Furthermore, supplying a current having a density not less than a predetermined value reverses the core.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: May 31, 2011
    Assignees: Kyoto University, The University of Electro-Communications, Osaka University, Tokyo Metropolitan University
    Inventors: Teruo Ono, Shinya Kasai, Kensuke Kobayashi, Yoshinobu Nakatani, Hiroshi Kohno, Gen Tatara
  • Publication number: 20110069541
    Abstract: The present invention uses a ferromagnetic thin wire having a domain wall inside, with the magnetic moment at the center thereof being perpendicular to the longitudinal axis of the thin wire. With the domain wall being fixed by a domain wall fixation device (e.g. antiferromagnetic thin wires) so that the domain wall is prevented from moving in the ferromagnetic thin wire, when a direct current is supplied, the magnetic moment rotates in the immobilized domain wall. This rotation of the moment can be detected by a TMR element or the like. This configuration of the ferromagnetic thin wire element can be directly used to create a microwave oscillator or magnetic memory.
    Type: Application
    Filed: April 21, 2008
    Publication date: March 24, 2011
    Applicants: KYOTO UNIVERSITY, THE UNIVERSITY OF ELECTRO-COMMUNICATIONS
    Inventors: Teruo Ono, Yoshinobu Nakatani
  • Publication number: 20100215851
    Abstract: A method of producing core/shell composite nano-particles exhibiting superior characteristics, by using as cores nano-particles heat treated in advance so as to give them a specific crystal structure in a state using a barrier layer to prevent sintering and forming shells on their surface, which eliminates hindrances to the shell forming reaction due to the phase transfer catalyst or other strongly sticky dispersant, is provided.
    Type: Application
    Filed: April 25, 2007
    Publication date: August 26, 2010
    Inventors: Tetsuya Shoji, Naoki Nakamura, Akira Kato, Shinpei Yamamoto, Mikio Takano, Teruo Ono
  • Publication number: 20100157662
    Abstract: In one embodiment of the present invention, an MRAM is an MRAM including: a plurality of write word lines; a plurality of bit lines provided so as to intersect with the write word lines; and TMR elements provided at respective intersections of the write word lines and the bit lines. Each of the TMR elements includes a first ferromagnetic layer of which magnetization direction is variable, a second ferromagnetic layer of which magnetization direction is fixed, and a tunnel wall which is sandwiched between the first ferromagnetic layer and the second ferromagnetic layer. The bit line is provided, for example, so as to bulge in the direction in which the write word line extends at the intersection of the bit line and the write word line, so that a magnetic wall is introduced at a desired position of the bit line. Further, a current fed through the bit line is fed through the first ferromagnetic layer at the time of data writing. This makes it possible to provide the MRAM having a gigabit-class capacity.
    Type: Application
    Filed: April 26, 2006
    Publication date: June 24, 2010
    Inventors: Teruo Ono, Akinobu Yamaguchi, Saburo Nasu
  • Publication number: 20090180311
    Abstract: The present invention provides a novel element capable of simply controlling an in-plane rotational motion of a core (a rising spot of a magnetization) generated in the center of a ferromagnetic dot made by forming a ferromagnetic material into a nanosized disk shape. In addition, the present invention is achieved to provide a binary information memory element using a core, including a ferromagnetic dot, made of a disk-shaped ferromagnetic material, with a magnetic structure of a magnetic vortex structure, and a current supplier for supplying an alternating current with a predetermined alternating current in the radial direction of the ferromagnetic dot. In the case where the frequency of the current resonates with the intrinsic frequency of the ferromagnetic dot, it is possible to rotate the core in the plane of the dot. Since the core leaks a magnetic field, a microscopic actuator such as a motor can be obtained by using this element.
    Type: Application
    Filed: March 1, 2007
    Publication date: July 16, 2009
    Applicants: Kyoto University, The University of Electro-Communications, Osaka University, Tokyo Metropolitan University
    Inventors: Teruo Ono, Shinya Kasai, Kensuke Kobayashi, Yoshinobu Nakatani, Hiroshi Kohno, Gen Tatara
  • Publication number: 20070259133
    Abstract: A FePt alloy nanoparticle, which is expected to be a promising material used for an ultra-high-density magnetic recording medium of the next generation, is ordered by heat treatment to have high magnetic anisotropy, but there has been a problem that the particles are coalesced with each other and agglomerate during the heat treatment. According to the present invention, each particle of the alloy nanoparticles is covered with a coating such as SiO2, and thereafter a heat treatment for ordering is carried out. In this method, the alloy nanoparticles do not coalesce with each other even if the heat treatment is performed at such a high temperature as to allow all the particles to be fully ordered. After the heat treatment, only the coating is removed using an acid or alkali solution so that it is possible to obtain ordered alloy phase nanoparticles which are ordered and dispersible in various solutions.
    Type: Application
    Filed: December 7, 2005
    Publication date: November 8, 2007
    Applicant: KYOTO UNIVERSITY
    Inventors: Teruo Ono, Shinpei Yamamoto, Yasumasa Morimoto, Mikio Takano
  • Patent number: 6555763
    Abstract: A multilayered circuit board for a semiconductor chip module includes an underlying board, insulating layers, fixed-potential wiring layers, via holes, and metal layers. The underlying board has a major surface made of a metal material to which a fixed potential is applied. The insulating layers are stacked on the major surface of the underlying board and have wiring layers formed on their surfaces. The fixed-potential wiring layers constitute part of the wiring layers formed on the insulating layers. The via holes are formed below the fixed-potential wiring layers to extend through the insulating layers. The metal layers are filled in the via holes so as to make upper ends be connected to the lower surfaces of the fixed-potential wiring layers. One of the insulating layers in contact with the major surface of the underlying board is formed on the underlying board while the lower end of the metal layer is in contact with the major surface of the underlying board.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: April 29, 2003
    Assignees: Fuchigami Micro Co., Ltd., NEC Compound Semiconductor Devices Ltd.
    Inventors: Koki Hirasawa, Teruo Ono
  • Patent number: 6351026
    Abstract: A multilayered wiring structure includes a lower wiring layer, an interlevel insulating layer, a filling layer, an upper wiring layer, and a plated layer. The lower wiring layer is formed on a lead frame through an insulating layer. The interlevel insulating layer is formed on the lower wiring layer to have a via hole at a predetermined region thereof to expose an upper portion of the lower wiring layer. The filling layer is made of a conductive material to fill the via hole. The upper wiring layer is formed on the interlevel insulating layer to have an opening above a portion where the via hole is formed. The plated layer is formed on the upper wiring layer to be connected to the filling layer. A method of manufacturing a multilayered wiring structure is also disclosed.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: February 26, 2002
    Assignee: NEC Corporation
    Inventors: Koki Hirasawa, Teruo Ono
  • Publication number: 20010038149
    Abstract: A multilayered wiring structure includes a lower wiring layer, an interlevel insulating layer, a filling layer, an upper wiring layer, and a plated layer. The lower wiring layer is formed on a lead frame through an insulating layer. The interlevel insulating layer is formed on the lower wiring layer to have a via hole at a predetermined region thereof to expose an upper portion of the lower wiring layer. The filling layer is made of a conductive material to fill the via hole. The upper wiring layer is formed on the interlevel insulating layer to have an opening above a portion where the via hole is formed. The plated layer is formed on the upper wiring layer to be connected to the filling layer. A method of manufacturing a multilayered wiring structure is also disclosed.
    Type: Application
    Filed: June 27, 2001
    Publication date: November 8, 2001
    Inventors: Koki Hirasawa, Teruo Ono
  • Patent number: 6274404
    Abstract: A multilayered wiring structure includes a lower wiring layer, an interlevel insulating layer, a filling layer, an upper wiring layer, and a plated layer. The lower wiring layer is formed on a lead frame through an insulating layer. The interlevel insulating layer is formed on the lower wiring layer to have a via hole at a predetermined region thereof to expose an upper portion of the lower wiring layer. The filling layer is made of a conductive material to fill the via hole. The upper wiring layer is formed on the interlevel insulating layer to have an opening above a portion where the via hole is formed. The plated layer is formed on the upper wiring layer to be connected to the filling layer. A method of manufacturing a multilayered wiring structure is also disclosed.
    Type: Grant
    Filed: September 22, 1999
    Date of Patent: August 14, 2001
    Assignee: NEC Corporation
    Inventors: Koki Hirasawa, Teruo Ono