Abstract: A semiconductor device with an expanded range of a recommended condition for an input voltage is disclosed. In embodiment, the semiconductor device having input protection on an input terminal thereto, includes: a semiconductor region having a first conducting type, first and second diffusion regions defined in the semiconductor region and respectively having a second conducting type, and a transistor formed by using the semiconductor region as a base, the first diffusion region as a collector, and the second diffusion region as an emitter. The first diffusion region is connected to one of a high-potential power supply and a low-potential power supply, the second diffusion region is connected to the input terminal, and the semiconductor region is connected to another power supply having a voltage high enough to reverse bias the junction between the semiconductor region and the first diffusion region.

Abstract: A semiconductor memory includes a power down pulse generating circuit having an output delay time which is dependent on the type of change or transition in an input signal. The pulse generating circuit generates a power down signal at different times depending on whether the input signal changes from a first level to a second level or from the second level to the first level to prevent the power down signal from being output twice when an input clock signal has a pulse width shorter than a normal pulse width thereof. The power down pulse generating circuit generates the power down signal in response to a signal from address transition detection circuitry, and causes data read/write circuitry and bit line pulse generating circuitry to become inactive to reduce power consumption. The bit line pulse generating circuitry generates reset signals which may be used to reset or precharge the bit lines at different timings to reduce peak current in the semiconductor memory.

Abstract: A output buffer circuit incorporates an output controller and voltage controller between a first and a second voltage potential to buffer the output of data produced by a semiconductor device. The output controller provides switching control signals to transistors in the voltage controller in order to prevent the first potential from being effected by the potential at the output of the output buffer.

Abstract: Disclosed is a semiconductor memory device which operates based on voltages from a high voltage power source and a low voltage power source. A plurality of memory cells are formed in a memory cell array. Plural pairs of bit lines are connected to the memory cells to transfer data signals read from the memory cells. A sense amplifier, which has a pair of input terminals, amplifies the data signal. A level shifter is selectively connected to plural pairs of bit lines to shift the level of the data signal of a selected pair of bit lines to a level near the operation point of the sense amplifier, and supplies a resultant data signal to the sense amplifier. The level shifter includes a first transistor for receiving the data signal, and a plurality of second transistors connected between the first transistor and the low voltage power source.

Abstract: A load generator is disclosed, which controls the voltage swing of the complementary logic signals generated in a semiconductor memory device. The load generator includes a first load circuit for controlling the potential levels of the signals appearing on a pair of complementary input signal lines. The first load circuit includes a first and second voltage dividers connected to the complementary input signal lines. Each of the first and second voltage dividers include a first voltage dividing transistor and a first voltage dividing resistive element connected in series between the semiconductor's low and high potential power supplies. The two first voltage dividing transistors are connected to each other in such a manner that a voltage, divided by one of the two transistors, is applied to the gate of the other transistor. The load generator further includes a second load circuit for controlling the potential levels of the signals appearing on a pair of complementary output signal lines.

Abstract: An initialization setting circuit (20) is adapted to set an initial condition of a latch circuit in a semiconductor device upon ON-set of the power supply, comprises a detecting circuit (TR1, TR2, R, 21) responsive to ON-set of power supply to detect the power source voltage (Vcc) reaching a given voltage, and an output level control circuit (22) responsive to the detecting signal output from the detecting circuit, for elevating up the level of an output signal of the initialization setting circuit to a high potential level or lowering the level of the output signal of the initialization setting circuit to a low potential level. By supplying the output signal controlled by said output level control circuit of the latch circuit as the power source voltage; the operation of the latch circuit is synchronized when the power source voltage is shut down, and a malfunction can be successfully prevented upon resetting of the power supply.

Abstract: A sense amplifier control circuit controls the activation and deactivation of sense amplifiers without a lowering of the operation speed of the sense amplifiers, correctly carries out a control operation without malfunctions, and is suitable for highly integrated circuits. The control circuit comprises a control unit, and each of the sense amplifiers comprises a pair of transistors forming a differential pair and a constant current source transistor connected to a common node of the differential pair. The control unit is connected to the constant current source transistors and generates a constant current source control signal in response to control signal indicating an activation or deactivation of the differential amplification operation of each differential pair.

Abstract: An integrated semiconductor circuit has a boost circuit that may improve boost operation speed. The boost circuit employs a P-channel type transistor as a driver. The back gate of the P-channel type transistor is connected to a charge-up circuit so that the back gate may be charged to a predetermined level before a boost signal is applied to the driver.

Abstract: An input signal is received by a level shift circuit to generate a plurality of level-shifted output signals which have different shift amounts to each other. A switch circuit, selectively outputs the level-shifted output signals in response to a logic level of the input signal. The switch circuit selects a signal having a higher potential from the level-shifted output signals when the logic level of the input signal indicates a first level, and selects a signal having a lower potential from the level-shifted output signals when the logic level of the input signals indicates a second level.

Abstract: A delay circuit having two or more first switching transistors connected in series between an output terminal and a power source line, and two or more second switching transistors connected in series between the output terminal and another power source line, the first and the second switching transistors operating in a complementary manner in response to an input signal, one or more nodes of each switching transistor being connected by one or more current paths each connecting at least one capacitor, whereby an input signal is transmitted to the output terminal at a specified interval defined by the capacitance of the capacitor.

Abstract: A light source device disposing light sources at both end faces of the transparent plate in which a surface of the transparent plate in the side of an observer (front surface) is formed as the inclined and curved surface in view of limiting reduction in quantity of light per unit area at the observing area being far from the light source within a certain level, the one surface of the transparent plate is formed as the rough surface to diffuse the incident light, the other surface of the transparent plate is formed as a mirror-surface, and a reflecting layer having a high lightness is disposed at the lower side of the transparent plate in order to provide sufficient luminance for observers.

Abstract: A static-type semiconductor memory device having a three-layer structure: gate-electrode wiring lines being formed from a first conductive layer of, for example, polycrystalline silicon; word lines, ground lines, and power supply lines being formed from a second conductive layer of, for example, aluminum; and bit lines being formed from a third conductive layer of, for example, aluminum. The bit lines extending in a column direction, and the ground lines extending in a row direction. Thus, providing an improved degree of integration, an improved operating speed, an improved manufacturing yield, and a countermeasure for soft errors due to alpha particles.

Abstract: A semiconductor memory device in which the memory cells are arranged in matrix form and in which, when a defective cell exists among the memory cells and a row or column containing the defective cell is selected, the selected row or column is switched to a predetermined redundant row or a predetermined redundant column additionally and independently provided. A plurality of switching circuits are provided, each of the switching circuits being connected to the output of the decoder circuit, which select the row or the column of memory cells. A fusing circuit is connected to each of the switching circuits, and when the fuse in the fusing circuit is disconnected, the row or the column containing the defective cell is switched to the redundant row or the redundant column.

Abstract: In a static semiconductor memory device incorporating redundancy memory cells (C.sub.R0, C.sub.R1, . . . ), a connecting/disconnecting circuit is linked between a power supply terminal (V.sub.CC) and one of bit lines (B.sub.0, B.sub.0, . . . ), thereby reducing or cutting off a current flowing through a defective memory cell.

Abstract: A CMIS circuit device such as an IC chip in a semiconductor memory device, is made selectable by using at least two chip-select signals having opposite polarities. The CMIS circuit device has a chip-select control circuit for establishing a chip-selected state or a chip-unselected state upon receiving the abovementioned chip-select signals. The chip-select control circuit includes a CMIS inverter circuit which inverts one of the chip-select signals, and a CMIS logic gate circuit which receives an output signal from the CMIS inverter circuit and the other chip select signal or signals and outputs an internal chip-select control signal. The CMIS inverter circuit includes a CMIS inverter and one or more control transistors which receive the other chip-select signal or signals at the gates thereof and which are inserted in series between a power terminal of the CMIS inverter and a power source.

Abstract: A semiconductor memory device such as a static-type random-access memory device includes an address-change detection circuit which generates a pulse signal when an input address signal has changed and a latch circuit which temporarily stores the readout signal from the selected memory cell. The readout signal is input into the latch circuit in synchronization with the timing of the pulse signal or a short time after the pulse signal, and the readout data from the semiconductor memory device is obtained from the latch circuit, thereby increasing the time interval during which the readout data from the semiconductor memory device is available.

Abstract: A decoder circuit receives decoder inputs and producing decoder outputs. The decoder inputs are applied, as control inputs, to respective input transistors connected in parallel with each other. The outputs thereof are commonly connected to a node. The node is connected to a gate transistor and latch transistors. The gate transistor is operative to invert the level at the node momentarily every time the decoder circuit is switched from a nonselection state to a selection state. The latch transistors maintain the level at the node as the decoder output level.

Abstract: A static-type RAM device in which the amplitude of the data signal stored in a memory cell just after the writing in of data is completed is increased and the stability of the data stored in each memory cell is increased. The RAM device includes a bit-line pulling-up circuit for pulling up the potential of a bit line to a voltage which is approximately equal to or larger than the power supply voltage and a word-line pulling-up circuit for pulling up the potential of a selected word line to a voltage which is larger than the power supply voltage after the writing in of data is completed.

Abstract: A semiconductor device comprises a connection structure composed of a first conductive layer formed in or on a semiconductor substrate, a second conductive layer arranged adjacent to the first conductive layer, and a third conductive layer connecting the first conductive layer to the second conductive layer. The device of the present invention provides a contact structure which can be miniaturized.

Abstract: A logic circuit includes a plurality of input terminals (IN.sub.1, IN.sub.2, . . . ), an output terminal (OUT), a load (L), and at least two driver circuits (D.sub.1, D.sub.2, . . . ). Each of the driver circuits includes a plurality of gates connected in series, each gate being driven by one of the potentials at the input terminals. In addition, the first gates (Q.sub.11, Q.sub.22, . . . or Q.sub.11 ', Q.sub.22 ', . . . ) of the driver circuit connected directly to the output terminal are driven by different potentials at the input terminals.