Patents by Inventor Teruo Shoji
Teruo Shoji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7534629Abstract: By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.Type: GrantFiled: June 7, 2006Date of Patent: May 19, 2009Assignee: Renesas Technology Corp.Inventors: Teruo Shoji, Akio Hasebe, Yoshinori Deguchi, Motoji Murakami, Masayoshi Okamoto, Yasunori Narizuka, Susumu Kasukabe
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Patent number: 7423439Abstract: In a prove card comprising: a probe sheet having a contact terminal contacting with an electrode provided on a wafer, a wiring led from the contact terminal, and an electrode electrically connected to the wiring; and a multilayered wiring substrate having an electrode electrically connected to the electrode of the probe sheet, wherein a contact between the contact terminal and the electrode of the wafer is established by one or more adhesion holder for pressing, from the backside of a terminal group of the terminal contacts, the terminal group via a press block with a spring to contact with the electrode pad. A device in which the probe sheet is attached to the adhesion holder and a plurality of chips are tested simultaneously by combining the adhesion holder.Type: GrantFiled: October 5, 2006Date of Patent: September 9, 2008Assignee: Renesas Technology Corp.Inventors: Susumu Kasukabe, Teruo Shoji, Akio Hasebe, Yoshinori Deguchi, Yasunori Narizuka
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Patent number: 7351597Abstract: The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.Type: GrantFiled: May 18, 2007Date of Patent: April 1, 2008Assignee: Renesas Technology Corp.Inventors: Yuji Wada, Susumu Kasukabe, Takehiko Hasebe, Yasunori Narizuka, Akira Yabushita, Terutaka Mori, Akio Hasebe, Yasuhiro Motoyama, Teruo Shoji, Masakazu Sueyoshi
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Publication number: 20070218572Abstract: The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.Type: ApplicationFiled: May 18, 2007Publication date: September 20, 2007Inventors: Yuji Wada, Susumu Kasukabe, Takehiko Hasebe, Yasunori Narizuka, Akira Yabushita, Terutaka Mori, Akio Hasebe, Yasuhiro Motoyama, Teruo Shoji, Masakazu Sueyoshi
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Publication number: 20070207559Abstract: Any damage inflicted on test pads, inter-layer insulating films, semiconductor elements or wiring at the time of electrical inspection of semiconductor integrated circuit devices is to be reduced. Reinforcements having a substantially equal linear expansion ratio (coefficient of thermal expansion) relative to a wafer to be inspected are formed over an upper face of a thin film probe, grooves are cut in the reinforcements above the probes, a first elastomer which is softer than a second elastomer is so arranged as to fill the grooves and overflow the grooves by a prescribed quantity, a glass epoxy substrate, which is a multi-layered wiring board, is fitted over the second elastomer, and pads provided over an upper face of the glass epoxy substrate and bonding pads which are part of wirings belonging to the thin film probe are electrically connected by wires.Type: ApplicationFiled: May 4, 2007Publication date: September 6, 2007Inventors: Akio Hasebe, Yasunori Narizuka, Yasuhiro Motoyama, Teruo Shoji
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Patent number: 7235413Abstract: Any damage inflicted on test pads, inter-layer insulating films, semiconductor elements or wiring at the time of electrical inspection of semiconductor integrated circuit devices is to be reduced. Reinforcements having a substantially equal linear expansion ratio (coefficient of thermal expansion) relative to a wafer to be inspected are formed over an upper face of a thin film probe, grooves are cut in the reinforcements above the probes, a first elastomer which is softer than a second elastomer is so arranged as to fill the grooves and overflow the grooves by a prescribed quantity, a glass epoxy substrate, which is a multi-layered wiring board, is fitted over the second elastomer, and pads provided over an upper face of the glass epoxy substrate and bonding pads which are part of wirings belonging to the thin film probe are electrically connected by wires.Type: GrantFiled: October 20, 2004Date of Patent: June 26, 2007Assignee: Renesas Technology Corp.Inventors: Akio Hasebe, Yasunori Narizuka, Yasuhiro Motoyama, Teruo Shoji
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Patent number: 7219422Abstract: The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.Type: GrantFiled: January 29, 2004Date of Patent: May 22, 2007Assignee: Renesas Technology Corp.Inventors: Yuji Wada, Susumu Kasukabe, Takehiko Hasebe, Yasunori Narizuka, Akira Yabushita, Terutaka Mori, Akio Hasebe, Yasuhiro Motoyama, Teruo Shoji, Masakazu Sueyoshi
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Publication number: 20070103178Abstract: In a prove card comprising: a probe sheet having a contact terminal contacting with an electrode provided on a wafer, a wiring led from the contact terminal, and an electrode electrically connected to the wiring; and a multilayered wiring substrate having an electrode electrically connected to the electrode of the probe sheet, wherein a contact between the contact terminal and the electrode of the wafer is established by one or more adhesion holder for pressing, from the backside of a terminal group of the terminal contacts, the terminal group via a press block with a spring to contact with the electrode pad. A device in which the probe sheet is attached to the adhesion holder and a plurality of chips are tested simultaneously by combining the adhesion holder.Type: ApplicationFiled: October 5, 2006Publication date: May 10, 2007Inventors: Susumu Kasukabe, Teruo Shoji, Akio Hasebe, Yoshinori Deguchi, Yasunori Narizuka
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Publication number: 20060281222Abstract: By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.Type: ApplicationFiled: June 7, 2006Publication date: December 14, 2006Inventors: Teruo Shoji, Akio Hasebe, Yoshinori Deguchi, Motoji Murakami, Masayoshi Okamoto, Yasunori Narizuka
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Publication number: 20050095734Abstract: Any damage inflicted on test pads, inter-layer insulating films, semiconductor elements or wiring at the time of electrical inspection of semiconductor integrated circuit devices is to be reduced. Reinforcements having a substantially equal linear expansion ratio (coefficient of thermal expansion) relative to a wafer to be inspected are formed over an upper face of a thin film probe, grooves are cut in the reinforcements above the probes, a first elastomer which is softer than a second elastomer is so arranged as to fill the grooves and overflow the grooves by a prescribed quantity, a glass epoxy substrate, which is a multi-layered wiring board, is fitted over the second elastomer, and pads provided over an upper face of the glass epoxy substrate and bonding pads which are part of wirings belonging to the thin film probe are electrically connected by wires.Type: ApplicationFiled: October 20, 2004Publication date: May 5, 2005Inventors: Akio Hasebe, Yasunori Narizuka, Yasuhiro Motoyama, Teruo Shoji
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Publication number: 20040183556Abstract: Provided is a fabrication method of a semiconductor integrated circuit device which comprises forming a pushing mechanism by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal, placing an elastomer in the groove so that a predetermined amount exceeds the groove, and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. The present invention makes it possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.Type: ApplicationFiled: January 29, 2004Publication date: September 23, 2004Inventors: Yuji Wada, Susumu Kasukabe, Takehiko Hasebe, Yasunori Narizuka, Akira Yabushita, Terutaka Mori, Akio Hasebe, Yasuhiro Motoyama, Teruo Shoji, Masakazu Sueyoshi
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Patent number: 6142306Abstract: A carrier band of electronic parts which can carry electronic parts such as IC packages in good protected condition without spoiling the convenience of a carrier tape having convexities and sticking tape.Type: GrantFiled: December 18, 1998Date of Patent: November 7, 2000Assignee: Nissho CorporationInventors: Kazuhiro Mori, Eiji Itemadani, Souhei Tanaka, Osamu Hikita, Uzo Tomii, Kanji Sugio, Teruo Shoji, Yukihiko Asao