Patents by Inventor Teruo Tabata

Teruo Tabata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5141881
    Abstract: A method of making a semiconductor integrated circuit provided with an isolating region constituted of an upper and lower isolating regions, and integrated circuit element regions is disclosed, wherein: the lower isolating region is diffused upward to a depth of a little more than half the thickness of an epitaxial layer to link with the upper isolating region prior to a doping of the upper isolating region; the doping of the lower isolating region and integrated circuit element regions, is implemented by means of ion implantation through a resist film which is capable of blocking ions implanted and in which specified doping windows have been formed in advance, and a SiO.sub.2 film is used as a reference mask in an ion implanting step, and the respective borders of the upper isolating region and the specified regions of the circuit elements is determined by self-alignment.
    Type: Grant
    Filed: April 18, 1990
    Date of Patent: August 25, 1992
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kazuo Takeda, Toshimasa Sadakata, Teruo Tabata, Nobuyuki Sekikawa, Tadayoshi Takada, Yasuhiro Tamada, Yoshiaki Sano
  • Patent number: 4898839
    Abstract: A method of manufacturing a semiconductor integrated circuit comprises the steps of: forming an epitaxial layer covering a semiconductor substrate and buried layers; forming isolation regions dividing the epitaxial layer into a plurality of islands; forming a lower electrode region of an MIS type capacitor in one of the islands; forming a base region of a vertical bipolar transistor simultaneously with or independently from the lower electrode in another island; depositing a thin dielectric layer of the MIS type capacitor on a portion of the lower electrode region; thereafter selectively diffusing impurities into the surface layer of the base region so as to form an emitter region of the vertical bipolar transistor; and forming an upper electrode of the MIS type capacitor on the thin dielectric layer.
    Type: Grant
    Filed: November 15, 1988
    Date of Patent: February 6, 1990
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Chikao Fujinuma, Nobuyuki Sekikawa, Teruo Tabata, Tadayoshi Takada, Yoshiaki Sano, Toshimasa Sadakata
  • Patent number: 4780425
    Abstract: The present invention relates to a semiconductor device and a method of producing the same. According to this method, a lower diffusion layer of a double isolation diffusion area is attached to a surface of a substrate, an epitaxial layer being formed on the lower diffusion layer, the lower diffusion layer being largely outdiffused upwardly in the epitaxial layer and simultaneously an element diffusion area being deeply diffused from a surface of the epitaxial layer, and then an upper diffusion layer of the double isolation diffusion area being shallowly diffused from the surface of the epitaxial layer. Thus, the lateral expansion of the upper diffusion layer of the double isolation diffusion area can be suppressed and the integrated extent can be improved.
    Type: Grant
    Filed: November 12, 1987
    Date of Patent: October 25, 1988
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Teruo Tabata