Patents by Inventor Teruo Tanimoto

Teruo Tanimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9753872
    Abstract: A control device is coupled to node devices and one or more input and output devices, each node device including an arithmetic processing unit and a memory. The control device is configured to store history information including an entry in which device identification information for identifying the input and output device that is accessed based on a request corresponds to node identification information for identifying a node device of the node devices which is a transmission source of the request; determine the node identification information corresponding to the device identification information that indicates an input and output device which outputs a memory access request to the memory based on search of the entry in the history information; generate a packet in which the determined node identification information is set to a memory access destination based on the memory access request; and output the generated packet.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: September 5, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Teruo Tanimoto
  • Patent number: 9509623
    Abstract: An information processing device configured to process packets received from a plurality of sources includes a buffer configured to store the packets received from the plurality of sources, a first processing unit configured to transmit, to a source of a first packet, a request to stop transmission of the first packet and configured to discard the first packet if the buffer does not have an available region for storing the first packet received, and a second processing unit configured to transmit, to the source of the first packet, a request to retransmit the first packet if the buffer has the available region.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: November 29, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Teruo Tanimoto
  • Publication number: 20160328276
    Abstract: A system includes: a first device configured to transmit a first request; and a second device coupled to the first device, the second device including a processor configured to execute a program, a memory, and a communicating device. The communicating device is configured to: receive the first request, when a lock variable is not stored at a given address in the memory, write the lock variable at the given address, and perform processing of the first request, and when the communicating device is unable to write the lock variable at the given address within a set time due to the lock variable stored at the given address, notify an interrupt to the program, and hand over the processing of the first request to the processor.
    Type: Application
    Filed: April 27, 2016
    Publication date: November 10, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Teruo Tanimoto, TAKASHI MIYOSHI
  • Publication number: 20160112318
    Abstract: A system includes a first apparatus coupled to a second apparatus through communication paths. The first apparatus generates leading packets, each including destination information to identify the second apparatus in leading data among data read from a first memory based on a memory transfer request the second apparatus being a destination of the data specified by the memory transfer request, transmits the leading packets to the communication paths, respectively, generates last packets including the destination information in last data among the data read from the first memory based on the memory transfer request, and transmits the last packets to the communication paths, respectively. The second apparatus counts the last packets received through the communication paths, and control to store the last data included in the received last packets in a second memory when the number of the last packets counted coincides with the number of the communication paths.
    Type: Application
    Filed: October 15, 2015
    Publication date: April 21, 2016
    Applicant: FUJITSU LIMITED
    Inventor: Teruo TANIMOTO
  • Publication number: 20150370732
    Abstract: A control device is coupled to node devices and one or more input and output devices, each node device including an arithmetic processing unit and a memory. The control device is configured to store history information including an entry in which device identification information for identifying the input and output device that is accessed based on a request corresponds to node identification information for identifying a node device of the node devices which is a transmission source of the request; determine the node identification information corresponding to the device identification information that indicates an input and output device which outputs a memory access request to the memory based on search of the entry in the history information; generate a packet in which the determined node identification information is set to a memory access destination based on the memory access request; and output the generated packet.
    Type: Application
    Filed: June 4, 2015
    Publication date: December 24, 2015
    Applicant: Fujitsu Limited
    Inventor: Teruo TANIMOTO
  • Publication number: 20150220481
    Abstract: A processor core executes an arithmetic processing, and allocates an area in a memory with respect to a process of reading data and writing data. An MMU receives a use request for the memory form the processor core 1 and performs the process on the memory by using a first area of the memory allocated by the processor core. An RDMA module receives an instruction to perform a data transfer process between the memory and another memory from the processor core, requests, when the area for the data transfer has not been allocated, the processor core to execute the allocation, and performs the data transfer process by using a second area that is allocated by the processor core.
    Type: Application
    Filed: December 19, 2014
    Publication date: August 6, 2015
    Inventor: Teruo Tanimoto
  • Publication number: 20140362867
    Abstract: An information processing device configured to process packets received from a plurality of sources includes a buffer configured to store the packets received from the plurality of sources, a first processing unit configured to transmit, to a source of a first packet, a request to stop transmission of the first packet and configured to discard the first packet if the buffer does not have an available region for storing the first packet received, and a second processing unit configured to transmit, to the source of the first packet, a request to retransmit the first packet if the buffer has the available region.
    Type: Application
    Filed: April 22, 2014
    Publication date: December 11, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Teruo TANIMOTO
  • Patent number: 4142713
    Abstract: In the method of heat-treatment of welded pipe having a reinforcement weld bead therealong by heating the pipe by using an induction heating device and then by cooling it, the bead which has just been heated by the induction heating device, is further heated by a bead heater to a temperature such that the temperature difference between the metal of the pipe and the bead is smaller than a temperature difference which will produce a bad influence on the quality of the pipe.
    Type: Grant
    Filed: May 16, 1977
    Date of Patent: March 6, 1979
    Assignee: Nippon Steel Corporation
    Inventors: Hajime Nakasugi, Tsurugi Kimura, Teruo Tanimoto, Tsutomu Sakimoto