Patents by Inventor Teruo Tazunoki

Teruo Tazunoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080309744
    Abstract: A liquid-ejecting head is provided whereby it is possible to eject both a main droplet and a satellite in the desired ejection direction, and furthermore, wherein no bias exists in the lifetimes of the heaters of a tip A and a tip B. In order to do so, a stopper is formed inside the ejection nozzle, the stopper limiting the movement of movable valves during bubble formation.
    Type: Application
    Filed: June 11, 2008
    Publication date: December 18, 2008
    Applicant: CANON FINETECH INC.
    Inventors: Kayo Mukai, Toshio Kashino, Teruo Tazunoki
  • Patent number: 5031018
    Abstract: A basic cell of a gate array device comprises a substrate, a plurality of source/drain diffusion regions being formed in the substrate, at least one gate electrode being located between the adjacent source/drain diffusion regions, a substrate contact region being formed in the substrate and being located in the vicinity of the source/drain diffusion regions, and an insulation film being provided on the source/drain regions and the gate electrode and being provided with contact hole forming regions at which contact holes are to be formed so as to form a plurality of interconnecting channels for making an electric connection between desired regions. Each of the source/drain diffusion regions adjacent to the substrate contact region has a narrower portion located under one interconnecting channel specifically for making one substrate contact and a wider portion located under the other interconnecting channels.
    Type: Grant
    Filed: March 10, 1988
    Date of Patent: July 9, 1991
    Assignee: Fujitsu Limited
    Inventors: Takehide Shirato, Teruo Tazunoki
  • Patent number: 4914503
    Abstract: A semiconductor device comprises a semiconductor chip having main power supply lines which are arranged in peripheral regions in the vicinity of edges of the semiconductor chip and which are formed with multi-level metallization. The main power supply lines are formed with arrangements in that layers of the same potential face each other through an insulating layer in chip corner regions adjacent to corners of the semiconductor chip.
    Type: Grant
    Filed: August 11, 1987
    Date of Patent: April 3, 1990
    Assignee: Fujitsu Limited
    Inventors: Takehide Shirato, Teruo Tazunoki