Patents by Inventor Teruo Yokoyama

Teruo Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6395588
    Abstract: The impurity concentration contained in a layer on an electron supply layer of a high electron mobility field effect transistor is set in the range of 1˜1016 to 1˜1017 atoms/cm3, or the bandgap of a Schottky layer is set wider than that of the electron supply layer. Otherwise, in the steps of manufacturing the high electron mobility field effect transistor, after a silicon nitride film has been formed on a GaAs buried layer in which a second recess is formed and in a region on the inside of a first recess formed in a GaAs contact layer, the GaAs buried layer is still heated.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: May 28, 2002
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Tsutomu Igarashi, Kenji Arimochi, Teruo Yokoyama, Eizo Mitani, Shigeru Kuroda, Junichiro Nikaido, Yasunori Tateno
  • Publication number: 20020008248
    Abstract: The impurity concentration contained in a layer on an electron supply layer of a high electron mobility field effect transistor is set in the range of 1×1016 to 1×1017 atoms/cm3, or the bandgap of a Schottky layer is set wider than that of the electron supply layer. Otherwise, in the steps of manufacturing the high electron mobility field effect transistor, after a silicon nitride film has been formed on a GaAs buried layer in which a second recess is formed and in a region on the inside of a first recess formed in a GaAs contact layer, the GaAs buried layer is still heated.
    Type: Application
    Filed: June 15, 2001
    Publication date: January 24, 2002
    Applicant: Fujitsu Quantum Devices Limited
    Inventors: Tsutomu Igarashi, Kenji Arimochi, Teruo Yokoyama, Eizo Mitani, Shigeru Kuroda, Junichiro Nikaido, Yasunori Tateno
  • Patent number: 6329677
    Abstract: A field effect transistor has a semiconductor lamination structure, a Schottky contact gate electrode and source/drain ohmic electrodes disposed on both sides of the gate electrode on the lamination structure, source/drain regions disposed under the source/drain electrodes, a channel layer disposed in the lamination structure spaced apart from the principal surface and connecting the source/drain regions, a barrier layer disposed in the lamination structure between the channel layer and the principal surface and having a conduction band edge energy higher than the channel layer, and a pair of impurity doped regions formed in the barrier layer and channel layer continuously with the source/drain regions on both sides of the gate electrode, wherein a carrier density in the barrier layer is lower than a carrier density in the channel layer in the impurity doped region.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: December 11, 2001
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Hiroyuki Oguri, Teruo Yokoyama
  • Patent number: 6274893
    Abstract: The impurity concentration contained in a layer on an electron supply layer of a high electron mobility field effect transistor is set in the range of 1×1016 to 1×1017 atoms/cm3, or the bandgap of a Schottky layer is set wider than that of the electron supply layer.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: August 14, 2001
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Tsutomu Igarashi, Kenji Arimochi, Teruo Yokoyama, Eizo Mitani, Shigeru Kuroda, Junichiro Nikaido, Yasunori Tateno
  • Patent number: 6153897
    Abstract: A laminated layer having a layer containing Al (In) and a layer not containing Al (In) alternately laminated one upon another is plasma etched by an etchant gas which can etch both the layers containing and not containing Al (In). An additive gas containing F is added to the etchant gas while a layer not containing Al (In) is etched. When the surface of the layer containing Al (In) is exposed, fluorides are formed on the surface of the layer containing Al (In) and the etching is automatically stopped. An emission peak specific to Al (In) is monitored to detect which layer is presently etched.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: November 28, 2000
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Oguri, Teruo Yokoyama
  • Patent number: 6075262
    Abstract: A compound semiconductor transistor has a structure in which a first insulating film is formed only under a overhang of a gate electrode an upper part of which is formed widely, and a second insulating film for threshold voltage adjustment is formed on the side of a gate electrode and the first insulating film.
    Type: Grant
    Filed: July 25, 1997
    Date of Patent: June 13, 2000
    Assignee: Fujitsu Limited
    Inventors: Toshiaki Moriuchi, Teruo Yokoyama
  • Patent number: 5837617
    Abstract: A laminated layer having a layer containing Al (In) and a layer not containing Al (In) alternately laminated one upon another is plasma etched by an etchant gas which can etch both the layers containing and not containing Al (In). An additive gas containing F is added to the etchant gas while a layer not containing Al (In) is etched. When the surface of the layer containing Al (In) is exposed, fluorides are formed on the surface of the layer containing Al (In) and the etching is automatically stopped. An emission peak specific to Al (In) is monitored to detect which layer is presently etched.
    Type: Grant
    Filed: April 1, 1994
    Date of Patent: November 17, 1998
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Oguri, Teruo Yokoyama
  • Patent number: 5686325
    Abstract: A compound semiconductor transistor has a structure in which a first insulating film is formed only under a overhang of a gate electrode an upper part of which is formed widely, and a second insulating film for threshold voltage adjustment is formed on the side of a gate electrode and the first insulating film.
    Type: Grant
    Filed: September 21, 1995
    Date of Patent: November 11, 1997
    Assignee: Fujitsu Limited
    Inventors: Toshiaki Moriuchi, Teruo Yokoyama
  • Patent number: 5276340
    Abstract: A semiconductor integrated circuit including therein a plurality of active devices comprises a semiconductor substrate, a first buffer layer on the substrate, a second buffer layer provided on the substrate and incorporating therein defects with a concentration level substantially larger than the concentration level of the defects in the first buffer layer; a device layer provided on the second buffer layer and being provided with the active devices, and a plurality of unconductive, device isolation regions formed between the active devices such that the device isolation region extends from an upper surface of the device layer toward the substrate at least beyond a lower surface of the device layer.
    Type: Grant
    Filed: November 13, 1992
    Date of Patent: January 4, 1994
    Assignee: Fujitsu Limited
    Inventors: Teruo Yokoyama, Masahisa Suzuki, Tomonori Ishikawa, Takeshi Igarashi