Patents by Inventor Teruo Yoneyama

Teruo Yoneyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4095095
    Abstract: On the surface of a semiconductor wafer there is formed a binary-coded pattern which has high and low reflection portions and which contains an item of wafer processing information. A scanning device is provided to scan such patterns on individual wafers in order to obtain items of scanned information. Further a control device is provided to store the items of wafer processing information. Upon receipt of an item of scanning information, the control device produces a control signal which corresponds to the item of scanning information. The control signal is supplied to one of wafer processors, which effects on the semiconductor wafer the process necessary to manufacture a semiconductor device.
    Type: Grant
    Filed: March 30, 1977
    Date of Patent: June 13, 1978
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Hisashi Muraoka, Teruo Yoneyama