Patents by Inventor Terutaka Okada

Terutaka Okada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240117250
    Abstract: A photo-alignment thermosetting liquid crystal composition including: a side-chain liquid crystal polymer which contains a liquid crystal constitutional unit containing a liquid crystal moiety in a side chain and a non-liquid crystal constitutional unit containing an alkylene group in a side chain, a copolymer which contains a photo-alignment constitutional unit containing a photo-alignment group in a side chain and a thermally crosslinkable constitutional unit containing a thermally crosslinkable group in a side chain, and in which the photo-alignment constitutional unit does not contain a linear alkylene group between the photo-alignment group and a monomer unit, and a thermal crosslinking agent for bonding to the thermally crosslinkable group of the thermally crosslinkable constitutional unit.
    Type: Application
    Filed: January 21, 2022
    Publication date: April 11, 2024
    Applicant: DAI NIPPON PRINTING CO., LTD.
    Inventors: Shunsuke IRIE, Ken-ichi OKUYAMA, Kazuyuki OKADA, Terutaka TAKAHASHI, Kei AKIYAMA
  • Patent number: 6649931
    Abstract: A semiconductor device includes a first semiconductor chip having a non-volatile memory array which has a first memory area for storing input information of usual operation, and a second memory area for storing historical information of an electrical characteristic test of the first memory area. The device further includes a second semiconductor chip having a volatile memory array with a third memory area for storing input information of usual operation. Historical information of an electrical characteristic test of the third memory area of the second semiconductor chip is stored into the second memory area of the first semiconductor chip.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: November 18, 2003
    Assignees: Hitachi, Ltd., Akita Electronics Co., Ltd.
    Inventors: Kazuki Honma, Terutaka Okada, Fumiaki Kitajima, Takahiro Hatazawa, Hiroyuki Motomatsu, Katsuhiro Haruyama
  • Publication number: 20030013249
    Abstract: There is provided an electrical characteristic test technique for a semiconductor device that can shorten the time required for a next probe test after a wafer level burn-in test, prevent leak of defective product to an assembling process and moreover easily realizes the analysis of cause for generation of a fault after delivery of products to customers.
    Type: Application
    Filed: September 17, 2002
    Publication date: January 16, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Kazuki Honma, Terutaka Okada, Fumiaki Kitajima, Takahiro Hatazawa, Hiroyuki Motomatsu, Katsuhiro Haruyama
  • Publication number: 20020061606
    Abstract: There is provided an electrical characteristic test technique for a semiconductor device that can shorten the time required for a next probe test after a wafer level burn-in test, prevent leak of defective product to an assembling process and moreover easily realizes the analysis of cause for generation of a fault after delivery of products to customers.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 23, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Kazuki Honma, Terutaka Okada, Fumiaki Kitajima, Takahiro Hatazawa, Hiroyuki Motomatsu, Katsuhiro Haruyama
  • Patent number: 4947373
    Abstract: A semiconductor memory is provided with a first memory cell group, a second memory cell group, a first register for a serial output operation for holding information related to the first memory cell group, a second register for a serial output operation for holding information related to the second memory cell group, and transfer means for transferring information related to either the first or second memory cell group to either the first or second serial output register. By virtue of this arrangement, while the information transferred to the first serial output register is being serially output therefrom, information can simultaneously be transferred to the second serial output register by the transfer means.
    Type: Grant
    Filed: December 17, 1987
    Date of Patent: August 7, 1990
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Yasunori Yamaguchi, Katsuyuki Sato, Jun Mitake, Hitoshi Kawaguchi, Masahiro Yoshida, Terutaka Okada, Makoto Morino, Tetsuya Saeki, Yosuke Yukawa, Osamu Nagashima