Patents by Inventor Terutaka Tateishi

Terutaka Tateishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and circuit for checking storage protection by pre-checking an access request key
    Patent number: 4954982
    Abstract: A storage-protection-check circuit includes a storage key corresponding to the unit area of a storage region, the storage key being stored in a key storage. The value of the access request key having an access request corresponding to the storage region is checked. When the access request key has a specified value, the storage region is accessed without reading the storage key out of the key storage.
    Type: Grant
    Filed: February 24, 1989
    Date of Patent: September 4, 1990
    Assignee: Fujitsu Limited
    Inventors: Terutaka Tateishi, Minoru Koshino, Kazuyuki Shimizu
  • Access control processing system in computer system
    Patent number: 4547848
    Abstract: This invention relates to a system for processing access requests issued from a plurality of access requesting units to a memory. In particular, in a storage system where the buffer storage BS and main storage MS are provided, access is first made to BS based on and access request and if the desired data is not found in BS, access is made to MS. When the desired data is not found in BS and access is then made to MS, acces to BS is carried out based on the next access request from the same access requesting unit in parallel with the access to MS by the first access request.
    Type: Grant
    Filed: June 30, 1983
    Date of Patent: October 15, 1985
    Assignee: Fujitsu Limited
    Inventors: Hidehiko Nishida, Minoru Koshino, Terutaka Tateishi, Akira Hattori
  • Key storage error processing system
    Patent number: 4514847
    Abstract: In a system which is provided with a key storage having stored therein main storage keys respectively corresponding to pages into which a main storage is split, each main storage key having at least a reference bit indicating whether the corresponding page is being accessed and a change bit indicating whether information has been written in the page, and in which a parity bit is added to each of the reference bits and the change bits to form the main storage key.
    Type: Grant
    Filed: September 20, 1982
    Date of Patent: April 30, 1985
    Assignee: Fujitsu Limited
    Inventors: Terutaka Tateishi, Kazuyuki Shimizu
  • Error processing system using two different types of replace logic
    Patent number: 4507729
    Abstract: A buffer storage which stores some of the blocks, into which a main storage is divided, and, when a new block is to be stored, designates a block to be replaced based on least recently used logic designating the least recently used block as the block to be replaced. When the buffer storage is put in a state in which the designation of the block to be replaced is not carried out, it is detected and logic different from the least recently used logic is used to designate the block to be replaced, thereby preventing failure of designation of the block to be replaced and consequently a block is replaced.
    Type: Grant
    Filed: August 25, 1982
    Date of Patent: March 26, 1985
    Assignee: Fujitsu Limited
    Inventors: Masanori Takahashi, Terutaka Tateishi