Patents by Inventor Teruto Hirota

Teruto Hirota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9524404
    Abstract: A program execution device capable of protecting a program against unauthorized analysis and alteration is provided. The program execution device includes an execution unit, a first protection unit, and a second protection unit. The execution unit executes a first program and a second program, and is connected with an external device that is capable of controlling the execution. The first protection unit disconnects the execution unit from the external device while the execution unit is executing the first program. The second protection unit protects the first program while the execution unit is executing the second program.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: December 20, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Hideki Matsushima, Teruto Hirota, Yukie Shoda, Shunji Harada
  • Publication number: 20160070938
    Abstract: A program execution device capable of protecting a program against unauthorized analysis and alteration is provided. The program execution device includes an execution unit, a first protection unit, and a second protection unit. The execution unit executes a first program and a second program, and is connected with an external device that is capable of controlling the execution. The first protection unit disconnects the execution unit from the external device while the execution unit is executing the first program. The second protection unit protects the first program while the execution unit is executing the second program.
    Type: Application
    Filed: November 16, 2015
    Publication date: March 10, 2016
    Inventors: Hideki MATSUSHIMA, Teruto HIROTA, Yukie SHODA, Shunji HARADA
  • Publication number: 20150372992
    Abstract: A content reproduction system includes an information processing terminal (102) and a secure device (103). The information processing terminal (102) receives a copyright protection application program (315) from an application distribution server (113). The copyright protection application program includes a first program having a first execution format executable in the information processing terminal (102) and a second program having a second execution format different from the first execution format and executable in the secure device (103). The second program is encrypted with a program key (515) held in the secure device (103). By extracting and executing the first program, the information processing terminal (102) extracts the second program and transmits the second program to the secure device (103).
    Type: Application
    Filed: August 25, 2015
    Publication date: December 24, 2015
    Inventors: Hideki MATSUSHIMA, Teruto HIROTA, Naoyoshi OTSUBO, Koichi MORIOKA, Natsume MATSUZAKI, Norio SANADA
  • Patent number: 9218485
    Abstract: A program execution device capable of protecting a program against unauthorized analysis and alteration is provided. The program execution device includes an execution unit, a first protection unit, and a second protection unit. The execution unit executes a first program and a second program, and is connected with an external device that is capable of controlling the execution. The first protection unit disconnects the execution unit from the external device while the execution unit is executing the first program. The second protection unit protects the first program while the execution unit is executing the second program.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: December 22, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Hideki Matsushima, Teruto Hirota, Yukie Shoda, Shunji Harada
  • Patent number: 9158924
    Abstract: An information processing apparatus that processes data to be protected is provided. The information processing apparatus includes a first storage unit, a second storage unit, and a cache control unit configured to cache data stored in the first storage unit into the second storage unit. The cache control unit is configured to lock a cache region in the second storage unit to thereby prevent cache data of the stored data from being written back into the first storage unit, the cache data being obtainable from the cache region in the second storage unit in which the stored data is cached, and write the data to be protected different from the stored data into the cache region in the second storage unit, after the cache region in the second storage unit is locked.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: October 13, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Manabu Maeda, Teruto Hirota, Hideki Matsushima
  • Patent number: 9152770
    Abstract: A content reproduction system includes an information processing terminal and a secure device. The information processing terminal receives a copyright protection application program from an application distribution server. The copyright protection application program includes a first program having a first execution format executable in the information processing terminal and a second program having a second execution format different from the first execution format and executable in the secure device. The second program is encrypted with a program key held in the secure device. By extracting and executing the first program, the information processing terminal extracts the second program and transmits the second program to the secure device. The secure device receives the second program from the information processing terminal, decrypts the second program using a program key stored in a key storing unit, and executes the second program.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: October 6, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hideki Matsushima, Teruto Hirota, Naoyoshi Otsubo, Koichi Morioka, Natsume Matsuzaki, Norio Sanada
  • Patent number: 8990487
    Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A size of a partition control area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: March 24, 2015
    Assignee: Panasonic Corporation
    Inventors: Takuji Maeda, Teruto Hirota
  • Publication number: 20140380503
    Abstract: A program execution device capable of protecting a program against unauthorized analysis and alteration is provided. The program execution device includes an execution unit, a first protection unit, and a second protection unit. The execution unit executes a first program and a second program, and is connected with an external device that is capable of controlling the execution. The first protection unit disconnects the execution unit from the external device while the execution unit is executing the first program. The second protection unit protects the first program while the execution unit is executing the second program.
    Type: Application
    Filed: September 11, 2014
    Publication date: December 25, 2014
    Inventors: Hideki MATSUSHIMA, Teruto HIROTA, Yukie SHODA, Shunji HARADA
  • Patent number: 8898666
    Abstract: A virtual machine system is provided with a processor having only two privileged modes, a low privileged mode and a high privileged mode, and achieves both a security function for protecting digital copyrighted works or the like and an operating system switching function that guarantees system reliability. The virtual machine system is provided with a first and a second processor and executes a hypervisor on the first processor in the high privileged mode. An operating system on the second processor is executed by cooperation between the hypervisor running on the first processor and a program running on the second processor in low privileged mode. This eliminates the need for running the hypervisor on the second processor in the high privileged mode, thus allowing for execution on the second processor in the high privileged mode of a program for implementing the security function.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: November 25, 2014
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Masahiko Saito, Teruto Hirota, Hiroo Ishikawa
  • Patent number: 8874938
    Abstract: A program execution device capable of protecting a program against unauthorized analysis and alteration is provided. The program execution device includes an execution unit, a first protection unit, and a second protection unit. The execution unit executes a first program and a second program, and is connected with an external device that is capable of controlling the execution. The first protection unit disconnects the execution unit from the external device while the execution unit is executing the first program. The second protection unit protects the first program while the execution unit is executing the second program.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: October 28, 2014
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Hideki Matsushima, Teruto Hirota, Yukie Shoda, Shunji Harada
  • Publication number: 20140237203
    Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A size of a partition control area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.
    Type: Application
    Filed: April 29, 2014
    Publication date: August 21, 2014
    Applicant: Panasonic Corporation
    Inventors: Takuji MAEDA, Teruto HIROTA
  • Patent number: 8751734
    Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A size of a partition control area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: June 10, 2014
    Assignee: Panasonic Corporation
    Inventors: Takuji Maeda, Teruto Hirota
  • Patent number: 8661553
    Abstract: A semiconductor memory card comprising a control IC 302, a flash memory 303, and a ROM 304. The ROM 304 holds information such as a medium ID 341 unique to the semiconductor memory card. The flash memory 303 includes an authentication memory 332 and a non-authentication memory 331. The authentication memory 332 can be accessed only by external devices which have been affirmatively authenticated. The non-authentication memory 331 can be accessed by external devices whether the external devices have been affirmatively authenticated or not. The control IC 302 includes control units 325 and 326, an authentication unit 321 and the like. The control units 325 and 326 control accesses to the authentication memory 332 and the non-authentication memory 331, respectively. The authentication unit 321 executes a mutual authentication with an external device.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: February 25, 2014
    Assignee: Panasonic Corporation
    Inventors: Teruto Hirota, Makoto Tatebayashi, Taihei Yugawa, Masataka Minami, Masayuki Kozuka
  • Publication number: 20130312064
    Abstract: A program execution device capable of protecting a program against unauthorized analysis and alteration is provided. The program execution device includes an execution unit, a first protection unit, and a second protection unit. The execution unit executes a first program and a second program, and is connected with an external device that is capable of controlling the execution. The first protection unit disconnects the execution unit from the external device while the execution unit is executing the first program. The second protection unit protects the first program while the execution unit is executing the second program.
    Type: Application
    Filed: July 26, 2013
    Publication date: November 21, 2013
    Applicant: Panasonic Corporation
    Inventors: Hideki MATSUSHIMA, Teruto HIROTA, Yukie SHODA, Shunji HARADA
  • Publication number: 20130268778
    Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.
    Type: Application
    Filed: May 21, 2013
    Publication date: October 10, 2013
    Inventors: Takuji MAEDA, Teruto HIROTA
  • Patent number: 8522053
    Abstract: A program execution device capable of protecting a program against unauthorized analysis and alteration is provided. The program execution device includes an execution unit, a first protection unit, and a second protection unit. The execution unit executes a first program and a second program, and is connected with an external device that is capable of controlling the execution. The first protection unit disconnects the execution unit from the external device while the execution unit is executing the first program. The second protection unit protects the first program while the execution unit is executing the second program.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: August 27, 2013
    Assignee: Panasonic Corporation
    Inventors: Hideki Matsushima, Teruto Hirota, Yukie Shoda, Shunji Harada
  • Patent number: 8473671
    Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A size of the partition control area of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: June 25, 2013
    Assignee: Panasonic Corporation
    Inventors: Takuji Maeda, Teruto Hirota
  • Publication number: 20130145477
    Abstract: A content reproduction system includes an information processing terminal and a secure device. The information processing terminal receives a copyright protection application program from an application distribution server. The copyright protection application program includes a first program having a first execution format executable in the information processing terminal and a second program having a second execution format different from the first execution format and executable in the secure device. The second program is encrypted with a program key held in the secure device. By extracting and executing the first program, the information processing terminal extracts the second program and transmits the second program to the secure device. The secure device receives the second program from the information processing terminal, decrypts the second program using a program key stored in a key storing unit, and executes the second program.
    Type: Application
    Filed: August 6, 2012
    Publication date: June 6, 2013
    Inventors: Hideki Matsushima, Teruto Hirota, Naoyoshi Otsubo, Koichi Morioka, Natsume Matsuzaki, Norio Sanada
  • Publication number: 20130111605
    Abstract: An information processing apparatus that processes data to be protected is provided. The information processing apparatus includes a first storage unit, a second storage unit, and a cache control unit configured to cache data stored in the first storage unit into the second storage unit. The cache control unit is configured to lock a cache region in the second storage unit to thereby prevent cache data of the stored data from being written back into the first storage unit, the cache data being obtainable from the cache region in the second storage unit in which the stored data is cached, and write the data to be protected different from the stored data into the cache region in the second storage unit, after the cache region in the second storage unit is locked.
    Type: Application
    Filed: May 2, 2012
    Publication date: May 2, 2013
    Inventors: Manabu Maeda, Teruto Hirota, Hideki Matsushima
  • Publication number: 20120331464
    Abstract: A virtual machine system is provided with a processor having only two privileged modes, a low privileged mode and a high privileged mode, and achieves both a security function for protecting digital copyrighted works or the like and an operating system switching function that guarantees system reliability. The virtual machine system is provided with a first and a second processor and executes a hypervisor on the first processor in the high privileged mode. An operating system on the second processor is executed by cooperation between the hypervisor running on the first processor and a program running on the second processor in low privileged mode. This eliminates the need for running the hypervisor on the second processor in the high privileged mode, thus allowing for execution on the second processor in the high privileged mode of a program for implementing the security function.
    Type: Application
    Filed: September 7, 2011
    Publication date: December 27, 2012
    Inventors: Masahiko Saito, Teruto Hirota, Hiroo Ishikawa