Abstract: A back annotation apparatus, which effectively carries out a back annotation, includes: a pre-layout simulation implementing part for detecting nodes of which the potential changes when a predetermined signal is applied to a logic circuit; a layout pattern verification implementing part for implementing a predetermined layout pattern verification for layout patterns of the logical circuit; a parasitic element extraction part connected to the pre-layout simulation implementing part which extracts parasitic elements from the nodes of which the potential changes; a net list generation part connected to the parasitic element extraction part for generating a net list which includes all the devices included in the layout pattern data and parasitic elements extracted in the parasitic element extraction part; and a post layout simulation implementing part connected to the net list generation part for implementing a post layout simulation by using the net list.

Abstract: Cross reference information is generated when comparing between a logic circuit and a layout in order to facilitate retrieval of optimum corresponding information of logic circuit and layout. A design verification apparatus includes a storage unit which stores logic circuit data and layout data on its layout pattern; an element recognition unit which recognizes the connection relation of elements, and a comparative verification unit. The comparative verification unit compares and verifies the correspondence between the connection relation of logic circuit and connection relation of layout based on the logic circuit data to merge elements of the logic circuit, and compares and verifies the correspondence of the connection relation of the merged elements. Further, the apparatus generates a cross reference information file specifying the corresponding relation of the elements and their wiring in first and second function units depending on the connection relation of the logic circuit.

Abstract: A semiconductor integrated circuit layout figure, inclusive of dimensional accuracy depending on the pattern shape, is efficiently verified with high accuracy. A layout verifying method for verifying whether or not a layout figure conforms to a design rule on the basis of vector data includes a reference vector classifying step for selecting and classifying a reference vector which serves as a reference for verification among vectors corresponding to sides, a verification object vector classifying step for selecting and classifying a object vector to be verified among the vectors corresponding to the sides and a verifying step for verifying a distance between each reference vector and the object vector to be verified selected among the vectors to be verified classified in correspondence with the direction of the reference vector.

Abstract: A back annotation apparatus, which effectively carries out a back annotation, includes: a pre-layout simulation implementing part for detecting nodes of which the potential changes when a predetermined signal is applied to a logic circuit; a layout pattern verification implementing part for implementing a predetermined layout pattern verification for layout patterns of the logical circuit; a parasitic element extraction part connected to the pre-layout simulation implementing part which extracts parasitic elements from the nodes of which the potential changes; a net list generation part connected to the parasitic element extraction part for generating a net list which includes all the devices included in the layout pattern data and parasitic elements extracted in the parasitic element extraction part; and a post layout simulation implementing part connected to the net list generation part for implementing a post layout simulation by using the net list.

Abstract: In a semiconductor circuit design verifying apparatus, a parasitic device retrieving part retrieves a parasitic device for a signal line connecting first stage active devices to a next stage active device. A time constant computing device computes a time constant between each first stage active device and the next stage active device including the parasitic device for the signal line between the first stage active devices and the next stage active device. An output data generating device outputs the time constant and information associated with the time constant to a user.