Abstract: A wiring board includes an insulating layer having a lower layer conductor on a lower surface thereof, a plurality of semiconductor element connection pads arranged in a lattice pattern in a semiconductor element mounting portion 1a having a quadrangular shape on the insulating layer, a via hole formed in the insulating layer below each of the semiconductor element connection pads, and a via conductor filled in the via hole and formed integrally with each of the semiconductor element connection pads. The wiring board includes a reinforcing via hole formed in the insulating layer in an outer region outside an arrangement region of the semiconductor element connection pads in corner portions of the semiconductor element mounting portion, and a reinforcing via conductor formed in the reinforcing via hole.

Abstract: A multilayer substrate with inner capacitors comprising a dielectric layer sandwiched between upper and lower insulating layers, a couple of printed electrodes in desired patterns within the thickness of the dielectric layer so as to form each capacitor at the portion of the dielectric layer corresponding to the electrodes, and a couple of leading terminals on one surface of the insulating layer, which communicate with the electrodes, the multilayer substrate being characterized in that the dielectric layer is composed of a ceramic composition mainly comprising MTiO.sub.3 -based ceramics (M represents one or several of Ba, Ca, Mg, La, Sr and Nd) and the insulating layer is composed of a ceramic composition mainly comprising MgO-SiO.sub.2 -CaO-based ceramics, which is defined by an area surrounded by the lines connecting points A, B, C, D, E, F and G as shown in FIG. 1 and listed below, wherein X, Y and Z respectively represent weight percent values of MgO, SiO.sub.2 and CaO at points A, B, C, D, E, F and G.