Patents by Inventor Teruyuki Maeda

Teruyuki Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240152013
    Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer i
    Type: Application
    Filed: January 19, 2024
    Publication date: May 9, 2024
    Inventors: Yoshihito HARA, Tohru DAITOH, Hajime IMAI, Teruyuki UEDA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA
  • Publication number: 20240150793
    Abstract: A vector that includes a nucleic acid sequence encoding protelomerase, a pair of nucleic acid sequences recognized by the protelomerase, and a nucleic acid sequence located between the pair of nucleic acid sequences and encoding a protein.
    Type: Application
    Filed: March 17, 2022
    Publication date: May 9, 2024
    Inventors: Teruyuki NISHI, Hirofumi MAEDA, Mitsuaki KITANO
  • Patent number: 11945960
    Abstract: The present invention relates to [1] an aqueous composition for ink-jet printing, containing a carbodiimide compound, a polyester resin and water; [2] a ink set for ink-jet printing containing an aqueous composition a containing a carbodiimide compound and water, and an aqueous composition b containing a polyester resin; [3] an ink set for ink-jet printing, containing the aforementioned aqueous composition for ink-jet printing and a water-based ink containing a colorant; and [4] an ink-jet printing method including the step 1 of ejecting a carbodiimide compound, a polyester resin, a colorant and water onto a surface of a printing medium by an ink-jetting method to print characters or images thereon; and the step 2 of subjecting the resulting printed characters or images to heat treatment at a temperature of 50 to 200° C. According to the aqueous composition of the present invention, it is possible to obtain a printed material that is excellent in rub fatness.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: April 2, 2024
    Assignee: KAO CORPORATION
    Inventors: Tomohiko Nagano, Teruyuki Fukuda, Takahiro Maeda
  • Patent number: 11927860
    Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer i
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 12, 2024
    Assignee: SHARP DISPLAY TECHNOLOGY CORPORATION
    Inventors: Yoshihito Hara, Tohru Daitoh, Hajime Imai, Teruyuki Ueda, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata
  • Patent number: 8902620
    Abstract: A power conditioner that suppresses distortion in a waveform of a sinusoidal generated voltage includes a first and second group including two switches each connected in inverse parallel and in series. The power conditioner alternately turns on and off both switches in the first group at a prescribed chopping frequency and alternately turns on and off both switches in the second group at a PWM frequency higher than the chopping frequency. If control is performed with a dead-time provided in the on/off timing for both switches in each group, the power conditioner adjusts and controls the on/off duty for the second group switches to correspond to the effective on drive in one switch by each diode during the dead-time for each switch in the first group.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 2, 2014
    Assignee: Omron Corporation
    Inventors: Masao Mabuchi, Kazuyoshi Imamura, Yasuhiro Tsubota, Takao Mizokami, Katsutaka Tanabe, Kotaro Nakamura, Teruyuki Maeda, Nobuyuki Toyoura, Mio Yamada
  • Patent number: 8570781
    Abstract: A power conditioner that suppresses generation of voltage spikes in a part of a generated sinusoidal voltage waveform. An offset between the timing of chopping, which depends on whether the voltage difference between the voltage of a third pulse voltage series and a sinusoidal voltage is positive or negative, and the timing of the switching between on/off duty cycles of a seventh and eighth switch is calculated, and the on/off duty cycles of the seventh and eighth switches are controlled on the basis of the timing offset.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: October 29, 2013
    Assignee: Omron Corporation
    Inventors: Masao Mabuchi, Kazuyoshi Imamura, Yasuhiro Tsubota, Takao Mizokami, Katsutaka Tanabe, Teruyuki Maeda, Kotaro Nakamura, Nobuyuki Toyoura, Mio Yamada
  • Publication number: 20050056907
    Abstract: There is provided a power transistor, as well as a semiconductor integrated circuit using the power transistor, in which malfunctions of parasitic PNP transistor and circuit malfunctions due to latch-up of peripheral circuits can be prevented. In a power transistor composed of a plurality of vertical PNP transistors arrayed on a P-type silicon substrate, a singularity or plurality of electrode portions of an N+ type buried layer formed to isolate the P-type silicon substrate and collectors of the plurality of vertical PNP transistors from each other are provided in an active region of the power transistor.
    Type: Application
    Filed: December 11, 2003
    Publication date: March 17, 2005
    Inventor: Teruyuki Maeda
  • Patent number: 6078095
    Abstract: A unit transistor forming a power transistor includes a collector region, a base region, and an emitter region. A base contact portion is formed at a prescribed portion on the base region. The base region has a convex portion, which projects in the direction toward the emitter region, at a portion where the base contact portion is formed. The emitter region has, at a portion where the base region projects, a convex portion projecting in the same direction as the direction in which the base region projects. The base region has, at a portion where the emitter region projects, a concave portion. A base resistor region is expanded by the convex portion provided at the emitter region, thereby increasing the resistance value of the base resistor R.sub.B. Consequently, a power transistor having a wide area of safety operation and capable of performing operation in a stable manner can be obtained without an increase in size of the transistor.
    Type: Grant
    Filed: May 29, 1997
    Date of Patent: June 20, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Teruyuki Maeda, Akio Nkajima