Abstract: The clock-synchronizing semiconductor memory device has a reset circuit which is capable of optionally setting a timing for releasing the device from a reset state and also keeping an output buffer in a high impedance state in a time period from a power-ON to a rise of an initial clock cycle of a clock signal “CLK”.

Abstract: A semiconductor memory device which prevents a sub word line from being incorrectly selected when a main word line breaks. A plurality of memory cells are connected to a main word decoder each via the main word line, a sub word decoder, and a sub word line. A plurality of redundant memory cells are connected to a redundant fuse circuit each via a redundant main word line, a redundant sub word decoder, and a redundant sub word line. A connection between the main word line and the sub word decoder and a connection between the redundant main word line and the redundant sub word decoder are each grounded by a high-resistance resistor.

Abstract: A semiconductor memory includes a pulse signal generator which receives a clock signal and outputs a first pulse signal and a second pulse signal respectively as a digit line recovery control signal and a word line selection signal. The pulse signal generator includes a first delay circuit and a second delay circuit connected in series, the first delay circuit providing a delay time for a pulse width of the recovery control signal, and the second delay circuit together with the first delay circuit providing a delay time for a pulse width of the word line selection signal. In response to the rising of the clock, the pulse signal generator outputs the digit line recovery control signal and the word line selection signal. Using these signals, digit line recovery is started immediately after cell node inversion during a write operation and word line is rendered non-selected after cell node is stabilized.