Patents by Inventor Tessil Thomas
Tessil Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972142Abstract: Circuitry comprises packet reception circuitry to receive a data communication packet with a storage classification from sending circuitry, the data communication packet including at least payload data and a target address for storage of the payload data; and storage control circuitry to control writing of the payload data of a given data communication packet by one or more storage devices selected from a set of two or more candidate storage devices each addressable by the target address, the storage control circuitry being responsive to the storage classification received with the given data communication packet and to respective persistence properties associated with the set of two or more candidate storage devices.Type: GrantFiled: December 29, 2020Date of Patent: April 30, 2024Assignee: ARM LIMITEDInventor: Tessil Thomas
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Patent number: 11914543Abstract: A data processing apparatus is provided, that includes communication configured for receiving, from an origin Peripheral Component Interconnect Express (PCIe) device, a translated PCIe packet comprising a destination field that comprises a physical address of a destination PCIe device. Permission circuitry transmits a permission check packet, separate to the translated PCIe packet, to a root port to determine whether the origin PCIe device has permission to access the destination PCIe device. Buffer circuitry stores the translated PCIe packet until a response to the permission check packet is received.Type: GrantFiled: December 6, 2021Date of Patent: February 27, 2024Assignee: Arm LimitedInventor: Tessil Thomas
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Patent number: 11860811Abstract: The present disclosure provides a system and methods for transferring data across an interconnect. One method includes, at a request node, receiving, from a source high speed serial controller, a write request from a source, dividing the write request into sequences of smaller write requests each having a last identifier, and sending, to a home node, the sequences of smaller write requests; and, at the home node, sending, to a destination high speed serial controller, the sequences of smaller write requests for assembly into intermediate write requests that are transmitted to a destination. Each sequence of smaller write requests is assembled into an intermediate write request based on the last identifier.Type: GrantFiled: March 23, 2022Date of Patent: January 2, 2024Assignee: Arm LimitedInventors: Arthur Brian Laughton, Tessil Thomas, Jacob Joseph
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Patent number: 11841752Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.Type: GrantFiled: June 3, 2021Date of Patent: December 12, 2023Assignee: Intel CorporationInventors: Tessil Thomas, Lokesh Sharma, Buck Gremel, Ian Steiner
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Patent number: 11803506Abstract: A data processing apparatus is provided that includes communication circuitry to transmit an interconnect message to a root port using a physical address mapped to the root port. Translation circuitry encapsulates, within the interconnect message to the root port, a Peripheral Component Interconnect Express (PCIe) message to a destination, the PCIe message having routing information encoded as a PCIe bus number associated with the destination.Type: GrantFiled: October 28, 2021Date of Patent: October 31, 2023Assignee: Arm LimitedInventors: Tessil Thomas, Anitha Kona, Jacob Joseph, Arthur Brian Laughton, Nandakishore Sastry
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Publication number: 20230305985Abstract: The present disclosure provides a system and methods for transferring data across an interconnect. One method includes, at a request node, receiving, from a source high speed serial controller, a write request from a source, dividing the write request into sequences of smaller write requests each having a last identifier, and sending, to a home node, the sequences of smaller write requests; and, at the home node, sending, to a destination high speed serial controller, the sequences of smaller write requests for assembly into intermediate write requests that are transmitted to a destination. Each sequence of smaller write requests is assembled into an intermediate write request based on the last identifier.Type: ApplicationFiled: March 23, 2022Publication date: September 28, 2023Applicant: Arm LimitedInventors: Arthur Brian Laughton, Tessil Thomas, Jacob Joseph
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Publication number: 20230267081Abstract: Peripheral components, data processing systems and methods of operating such peripheral components and data processing systems are disclosed. The systems comprise an interconnect comprising a system cache, a peripheral component coupled to the interconnect, and a memory coupled to the interconnect. The peripheral component has a memory access request queue for queuing memory access requests in a receipt order. Memory access requests are issued to the interconnect in the receipt order. A memory read request is not issued to the interconnect until a completion response for all older memory write requests has been received from the interconnect. The peripheral component is responsive to receipt of a memory read request to issue a memory read prefetch request comprising a physical address to the interconnect and the interconnect is responsive to the memory read prefetch request to cause data associated with the physical address in the memory to be cached in the system cache.Type: ApplicationFiled: February 23, 2022Publication date: August 24, 2023Inventors: Jacob JOSEPH, Tessil THOMAS, Arthur Brian LAUGHTON, Anitha KONA, Jamshed JALAL
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Publication number: 20230176993Abstract: A data processing apparatus is provided, that includes communication configured for receiving, from an origin Peripheral Component Interconnect Express (PCIe) device, a translated PCIe packet comprising a destination field that comprises a physical address of a destination PCIe device. Permission circuitry transmits a permission check packet, separate to the translated PCIe packet, to a root port to determine whether the origin PCIe device has permission to access the destination PCIe device. Buffer circuitry stores the translated PCIe packet until a response to the permission check packet is received.Type: ApplicationFiled: December 6, 2021Publication date: June 8, 2023Inventor: Tessil THOMAS
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Publication number: 20230140069Abstract: A data processing apparatus is provided that includes communication circuitry to transmit an interconnect message to a root port using a physical address mapped to the root port. Translation circuitry encapsulates, within the interconnect message to the root port, a Peripheral Component Interconnect Express (PCIe) message to a destination, the PCIe message having routing information encoded as a PCIe bus number associated with the destination.Type: ApplicationFiled: October 28, 2021Publication date: May 4, 2023Inventors: Tessil THOMAS, Anitha KONA, Jacob JOSEPH, Arthur Brian LAUGHTON, Nandakishore SASTRY
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Patent number: 11543868Abstract: In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.Type: GrantFiled: June 11, 2020Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Tessil Thomas, Robin A. Steinbrecher, Sandeep Ahuja, Michael Berktold, Timothy Y. Kam, Howard Chin, Phani Kumar Kandula, Krishnakanth V. Sistla
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Patent number: 11507514Abstract: An apparatus is provided, connectable to a memory and one or more peripherals. The apparatus includes translation request circuitry to receive a translation request from one of the peripherals to translate an input address within an input domain to an output address within an output domain. Signing circuitry generates a signature of at least part of the output address using a private key. Translation response circuitry responds to the translation request by transmitting to the one of the peripherals a translation response, including the output address and the signature. Gateway circuitry receives access requests to the memory. Each of the access requests comprises a desired memory address in the output domain and a signature of the desired memory address. The gateway performs validation of the signature of the desired memory address using the private key and in response to the validation of a given access request failing, performs an error action.Type: GrantFiled: February 5, 2020Date of Patent: November 22, 2022Assignee: Arm LimitedInventors: Tessil Thomas, Jan-Peter Larsson
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Patent number: 11392438Abstract: A data processing apparatus is provided comprising first processing circuitry. Interrupt generating circuitry generates an outgoing interrupt in response to the first processing circuitry becoming unresponsive. Interrupt receiving circuitry receives an incoming interrupt, which indicates that second processing circuitry has become unresponsive, and in response to receiving the incoming interrupt, causes the data processing apparatus to access data managed by the second processing circuitry.Type: GrantFiled: February 9, 2017Date of Patent: July 19, 2022Assignee: Arm LimitedInventors: Anitha Kona, Michael Wayne Garner, Randall L. Jones, Tessil Thomas, Seow Chuan Lim, Karthick Santhanam, Liana Christine Nicklaus
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Publication number: 20220206709Abstract: Circuitry comprises packet reception circuitry to receive a data communication packet with a storage classification from sending circuitry, the data communication packet including at least payload data and a target address for storage of the payload data; and storage control circuitry to control writing of the payload data of a given data communication packet by one or more storage devices selected from a set of two or more candidate storage devices each addressable by the target address, the storage control circuitry being responsive to the storage classification received with the given data communication packet and to respective persistence properties associated with the set of two or more candidate storage devices.Type: ApplicationFiled: December 29, 2020Publication date: June 30, 2022Inventor: Tessil Thomas
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Patent number: 11153231Abstract: An apparatus and method are provided for processing flush requests within a packet network. The apparatus comprises a requester device within the packet network arranged to receive a flush request generated by a remote agent requesting that one or more data items be flushed to a point of persistence. The requester device translates the flush request into a packet-based flush command conforming to a packet protocol of the packet network. A completer device within the packet network that is coupled to a persistence domain incorporating the point of persistence is arranged to detect receipt of the packet-based flush command, and then trigger a flush operation within the persistence domain to flush the one or more data items to the point of persistence. This provides a fast, hardware-based, mechanism for performing a flush operation within a persistence domain without needing to trigger software in the persistence domain to handle the flush to the point of persistence.Type: GrantFiled: July 19, 2019Date of Patent: October 19, 2021Assignee: Arm LimitedInventors: Tessil Thomas, Andrew Joseph Rushing
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Publication number: 20210294400Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.Type: ApplicationFiled: June 3, 2021Publication date: September 23, 2021Applicant: Intel CorporationInventors: Tessil Thomas, Lokesh Sharma, Buck Gremel, Ian Steiner
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Publication number: 20210240629Abstract: An apparatus is provided, connectable to a memory and one or more peripherals. The apparatus includes translation request circuitry to receive a translation request from one of the peripherals to translate an input address within an input domain to an output address within an output domain. Signing circuitry generates a signature of at least part of the output address using a private key. Translation response circuitry responds to the translation request by transmitting to the one of the peripherals a translation response, including the output address and the signature. Gateway circuitry receives access requests to the memory. Each of the access requests comprises a desired memory address in the output domain and a signature of the desired memory address. The gateway performs validation of the signature of the desired memory address using the private key and in response to the validation of a given access request failing, performs an error action.Type: ApplicationFiled: February 5, 2020Publication date: August 5, 2021Inventors: Tessil THOMAS, Jan-Peter LARSSON
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Patent number: 11079819Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.Type: GrantFiled: December 11, 2018Date of Patent: August 3, 2021Assignee: Intel CorporationInventors: Tessil Thomas, Lokesh Sharma, Buck Gremel, Ian Steiner
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Publication number: 20210021544Abstract: An apparatus and method are provided for processing flush requests within a packet network. The apparatus comprises a requester device within the packet network arranged to receive a flush request generated by a remote agent requesting that one or more data items be flushed to a point of persistence. The requester device translates the flush request into a packet-based flush command conforming to a packet protocol of the packet network. A completer device within the packet network that is coupled to a persistence domain incorporating the point of persistence is arranged to detect receipt of the packet-based flush command, and then trigger a flush operation within the persistence domain to flush the one or more data items to the point of persistence. This provides a fast, hardware-based, mechanism for performing a flush operation within a persistence domain without needing to trigger software in the persistence domain to handle the flush to the point of persistence.Type: ApplicationFiled: July 19, 2019Publication date: January 21, 2021Inventors: Tessil THOMAS, Andrew Joseph RUSHING
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Patent number: 10877530Abstract: In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.Type: GrantFiled: September 14, 2015Date of Patent: December 29, 2020Assignee: Intel CorporationInventors: Tessil Thomas, Robin A. Steinbrecher, Sandeep Ahuja, Michael Berktold, Timothy Y. Kam, Howard Chin, Phani Kumar Kandula, Krishnakanth V. Sistla
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Patent number: 10853271Abstract: An apparatus includes a first device configured to generate a transaction request targeted to a first address, a switch, coupled to the first device and configured to the route the transaction request, a port coupled to the peripheral switch and the data processing network, and a system memory management unit, coupled to the port. The system memory management unit is configured for receiving an address query for the first address from the peripheral port translating the first address to a second address, accessing attributes of a device associated with the second address and responding to the query. Access validation for the transaction request is confirmed or denied dependent upon the second address and the attributes of the device associated with the second address. The first device may be a peripheral device, the switch may be a peripheral switch and the port may be a peripheral port.Type: GrantFiled: August 3, 2018Date of Patent: December 1, 2020Assignee: Arm LimitedInventors: Tessil Thomas, Jamshed Jalal, Andrea Pellegrini, Anitha Kona