Abstract: A display control apparatus has a synchronizing signal generating section which generates a display synchronizing signal, a bus access control section which reads out video data for a plurality of system, one system at a time, from a local memory, a screen combining section which processes to combine video data which was readout, and video data for use in combining, sequentially, a buffer section which stores video data which was processed to be combined, and the video data for use in combining, a buffer control section which controls an access to the buffer section, a display IF section which reads out video data that the buffer section stores, and outputs the video data to each of display monitors in accordance with a display synchronizing signal, and display output selecting means which selects an output destination of video data for plural systems, which the display IF section outputs.

Abstract: An image processing apparatus carrying out a gamma correction for input data includes polygonal line approximating apparatus for carrying out the gamma correction by a polygonal line approximation, a look-up table partially storing gamma correction data corresponding to the input data, and a correction deciding portion and a selector which select the output of one of the polygonal line approximating apparatus and the look-up table corresponding to the input data.

Abstract: A screen synthesizing device includes: a display screen storing part for storing an image of a display screen; a layer reading control part for deciding whether or not a lower layer is transferred, deciding the validity and invalidity of a plurality of layers on the basis of a lower layer transfer deciding flag set by a decided result and parameters of a plurality of layers and controlling only valid layers to be read from a layer storing unit in accordance with the decision; and a synthesizing and calculating part for performing a synthesizing and calculating process only by the valid layers on the basis of a valid layer flag to update the image of the display screen stored in the display screen storing part.

Abstract: In a bus control device including an external interface, internal units, a memory interface, and an internal bus, the memory interface monitors the usage pattern of the internal bus, and in a case where the internal unit is not using the internal bus, a priority processing interval for allowing only the external interface to use the internal bus is set, thereby prohibiting the internal units from using the internal bus during the priority processing interval.

Abstract: A display control apparatus has a synchronizing signal generating section which generates a display synchronizing signal, a bus access control section which reads out video data for a plurality of system, one system at a time, from a local memory, a screen combining section which processes to combine video data which was readout, and video data for use in combining, sequentially, a buffer section which stores video data which was processed to be combined, and the video data for use in combining, a buffer control section which controls an access to the buffer section, a display IF section which reads out video data that the buffer section stores, and outputs the video data to each of display monitors in accordance with a display synchronizing signal, and display output selecting means which selects an output destination of video data for plural systems, which the display IF section outputs.

Abstract: An image processing apparatus carrying out a gamma correction for input data includes polygonal line approximating means for carrying out the gamma correction by a polygonal line approximation, a look-up table partially storing gamma correction data corresponding to the input data, and a correction deciding portion and a selector which select the output of one of the polygonal line approximating means and the look-up table corresponding to the input data.

Abstract: In a bus control device including an external interface, internal units, a memory interface, and an internal bus, the memory interface monitors the usage pattern of the internal bus, and in a case where the internal unit is not using the internal bus, a priority processing interval for allowing only the external interface to use the internal bus is set, thereby prohibiting the internal units from using the internal bus during the priority processing interval.