Abstract: According to one embodiment, a semiconductor integrated circuit includes: a logic circuit including a first scan chain configured to operate based on a first clock signal and a second scan chain configured to operate based on a second clock signal in a built-in self-test; a pattern generator configured to generate a test pattern and transmit the test pattern to the first and second scan chains; a compression circuit configured to compress first data received from the first and second scan chains; a clock select circuit configured to select one of the first and second clock signals and transmit the one of the first and second clock signals to the corresponding one of the first and second scan chains in the test; and a test control circuit configured to control the test and detect a fault in the logic circuit based on a result of the test.

Abstract: According to one embodiment, a semiconductor integrated circuit includes: a logic circuit including: a first scan chain and a second scan chain; a clock generator; and a test control circuit. The first scan chain includes: a first flip-flop having a first scan data input terminal and a first output terminal; and a first multiplexer. The first multiplexer is configured to electrically couple the first scan data input terminal to the first output terminal based on a first signal received from the test control circuit to form a first closed loop. The second scan chain includes a second flip-flop having a second scan data input terminal and a third output terminal that is not coupled to the second scan data input terminal.

Abstract: According to one embodiment, a semiconductor integrated circuit includes: a logic circuit including: a first scan chain and a second scan chain; a clock generator; and a test control circuit. The first scan chain includes: a first flip-flop having a first scan data input terminal and a first output terminal; and a first multiplexer. The first multiplexer is configured to electrically couple the first scan data input terminal to the first output terminal based on a first signal received from the test control circuit to form a first closed loop. The second scan chain includes a second flip-flop having a second scan data input terminal and a third output terminal that is not coupled to the second scan data input terminal.

Abstract: According to one embodiment, a semiconductor integrated circuit includes: a logic circuit including a first scan chain configured to operate based on a first clock signal and a second scan chain configured to operate based on a second clock signal in a built-in self-test; a pattern generator configured to generate a test pattern and transmit the test pattern to the first and second scan chains; a compression circuit configured to compress first data received from the first and second scan chains; a clock select circuit configured to select one of the first and second clock signals and transmit the one of the first and second clock signals to the corresponding one of the first and second scan chains in the test; and a test control circuit configured to control the test and detect a fault in the logic circuit based on a result of the test.

Abstract: An optical device and an optical transmitter are provided. The optical device includes a substrate, a first optical waveguide that may be formed in the substrate and may have a bending portion, and a second optical waveguide that intersects with the bending portion of the first optical waveguide, wherein a groove may be formed outside the bending portion of the first optical waveguide in the substrate.

Abstract: A semiconductor integrated circuit has one or more of scan chains each having series-connected flip-flops that exist in an internal circuit. Each scan chain is divided into a plurality of segments. Each segment is controllable a timing of a clock signal. The semiconductor integrated circuit has a clock gating circuit capable of being shared by the scan chains and configured to generate a plurality of clock signals for driving each segment, the clock gating circuit being provided for each scan chain, and a segment control signal generator configured to generate a control signal to be used when the clock gating circuit generates the clock signals so that an effect of a fault of the internal circuit is transferred through one of the segments and care bits corresponding to a next fault are captured in a corresponding segment.

Abstract: An optical modulation device includes: a crystal substrate having an electro-optic effect; an optical waveguide formed in the crystal substrate; an electrode formed on the crystal substrate, to apply an electric field to the optical waveguide; and a buried layer of low dielectric constant buried to avoid the optical waveguide, in at least one portion of a lower region of the electrode inside the crystal substrate, which is spaced from both of a front surface of the crystal substrate on which the electrode is formed and a rear surface thereof opposed to the front surface.

Abstract: A scan chain circuit causes a plurality of flip-flops to function as shift registers during execution of a scan test and can execute a scan shift that serially transfers test pattern data for the scan test. A clock gating circuit controls output of a pulse of a clock signal supplied to the scan chain circuit in accordance with a clock gating signal, whereas disables the clock gating signal based on a logic of a scan enable signal authorizing the scan shift. A first clock gating circuit included in the clock gating circuit disables the clock gating signal during the scan shift based on the logic of the scan enable signal and also inverts the clock signal and outputs a result of inverting.

Abstract: A semiconductor integrated circuit has a memory circuit having memory cells, a first register, a second register, a register selection circuit having an input to which an output of the first register and an output of the second register are connected, a memory bypass circuit which is located between a first switching circuit and a second switching circuit, and connected to the inputs and the outputs of the memory circuit. The register selection circuit is switched to the output signals of the first register when performing testing by way of the memory circuit, and switched to output signals of the second register when performing testing by way of the memory bypass circuit.

Abstract: An optical device and an optical transmitter are provided. The optical device includes a substrate, a first optical waveguide that may be formed in the substrate and may have a bending portion, and a second optical waveguide that intersects with the bending portion of the first optical waveguide, wherein a groove may be formed outside the bending portion of the first optical waveguide in the substrate.

Abstract: A semiconductor integrated circuit contains a logic circuit which operates upon receiving a clock; a logic built-in self test circuit which executes a built-in self test of said logic circuit, said logic built-in self test circuit having a pattern generator which generates a pattern to be input to said logic circuit, a pattern compactor which receives data output from said logic circuit that has received the pattern, compacts the data, and outputs a result, and a logic built-in self test control unit which controls operations of said pattern generator and said pattern compactor and controls an operation of causing a scan path in said logic circuit to shift upon receiving the pattern; a device circuit which operates upon receiving the clock; and a device circuit built-in self test circuit which executes a built-in self test of said device circuit.

Abstract: An optical device including (a) a substrate having an electro-optic effect; (b) a modulating optical waveguide formed on a surface layer portion of said substrate and forming an interference optical modulator for modulating input light; (c) an output optical waveguide formed on said surface layer portion of said substrate and connected to a downstream side portion of said modulating optical waveguide; and (d) a branching monitoring section for monitoring branched light of light propagated along said output optical waveguide and emitted from an outgoing end face of said substrate. The output waveguide has a reduced width region in which the waveguide width is reduced.

Abstract: The invention relates to an optical device which can increase the spread of a beam diameter in the depthwise direction by a simple configuration in comparison with that by prior art devices. The optical device includes a substrate, an optical path formed on the substrate, and a diffraction propagation region, provided between the optical path and an end face of the substrate, for propagating light emitted from the optical path with diffraction. The diffraction propagation region includes a first groove, formed therein, adapted to block part of components of the propagated light in a depthwise direction of the substrate.

Abstract: An optical modulation device includes: a crystal substrate having an electro-optic effect; an optical waveguide formed in the crystal substrate; an electrode formed on the crystal substrate, to apply an electric field to the optical waveguide; and a buried layer of low dielectric constant buried to avoid the optical waveguide, in at least one portion of a lower region of the electrode inside the crystal substrate, which is spaced from both of a front surface of the crystal substrate on which the electrode is formed and a rear surface thereof opposed to the front surface.

Abstract: Optical waveguides (A) and (B) of a Mach-Zehnder modulator is normally formed on a ?Z plane as an electric polarization non-inversion area. However, when the signal electrode 11 and the ground electrode 10 are provided asymmetrically on two waveguides, chirp occurs in output light, which is undesired. Therefore, these electrodes are provided symmetrically about the two waveguides. To effectively perform optical modulation, a part of the substrate in which an optical waveguide exists is to be electric polarization-inverted. As a result of the electric polarization inversion the optical waveguide is on the +Z plane. However, electric charge is accumulated on the +Z plane from unstable spontaneous electric polarization of an electric polarization inversion area, and has undesired influence on the performance of the optical modulator. Therefore, a conductive amorphous layer is formed on the surface of the electric polarization inversion area.

Abstract: A semiconductor integrated circuit has a memory circuit having memory cells, a first register, a second register, a register selection circuit having an input to which an output of the first register and an output of the second register are connected, a memory bypass circuit which is located between a first switching circuit and a second switching circuit, and connected to the inputs and the outputs of the memory circuit. The register selection circuit is switched to the output signals of the first register when performing testing by way of the memory circuit, and switched to output signals of the second register when performing testing by way of the memory bypass circuit.

Abstract: A scan chain circuit causes a plurality of flip-flops to function as shift registers during execution of a scan test and can execute a scan shift that serially transfers test pattern data for the scan test. A clock gating circuit controls output of a pulse of a clock signal supplied to the scan chain circuit in accordance with a clock gating signal, whereas disables the clock gating signal based on a logic of a scan enable signal authorizing the scan shift. A first clock gating circuit included in the clock gating circuit disables the clock gating signal during the scan shift based on the logic of the scan enable signal and also inverts the clock signal and outputs a result of inverting.

Abstract: A semiconductor integrated circuit has a memory circuit having memory cells, a first register, a second register, a register selection circuit having an input to which an output of the first register and an output of the second register are connected, a memory bypass circuit which is located between a first switching circuit and a second switching circuit, and connected to the inputs and the outputs of the memory circuit. The register selection circuit is switched to the output signals of the first register when performing testing by way of the memory circuit, and switched to output signals of the second register when performing testing by way of the memory bypass circuit.

Abstract: An optical device including (a) a substrate having an electro-optic effect; (b) an optical waveguide formed on a surface layer portion of said substrate and including an optical waveguide for performing optical modulation for light inputted to said substrate and an output optical waveguide and a monitoring optical waveguide branched from and connected to a downstream side portion of said modulating optical waveguide, said monitoring optical waveguide guiding light for monitoring optical modulation operation of said modulating optical waveguide; and (c) a reflecting portion being provided on the downstream side of said monitoring optical waveguide for reflecting light propagated along said monitoring optical waveguide, the width of a reflection face of said reflecting portion being substantially equal to the cut-out width of said monitoring optical waveguide.

Abstract: An optical device is disclosed which suppresses a bias shift which is a deviation of a phase relationship between output signal light and monitoring light. The optical device includes a substrate having an electro-optic effect, a modulating optical waveguide formed on a surface layer portion of the substrate and forming an interference optical modulator for modulating input light, and an output optical waveguide and a monitoring optical waveguide each formed on the surface layer portion of the substrate and branched from and connected to a downstream side portion of the modulating optical waveguide. The monitoring optical waveguide guides light for monitoring optical modulation operation of the modulating optical waveguide. The monitoring optical waveguide has a reduced width region which has a reduced waveguide width.