Patents by Inventor Tetsu Ishiyama

Tetsu Ishiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6720644
    Abstract: A semiconductor formed by mounting a semiconductor chip on an interposer substrate and the manufacturing method therefor is disclosed. This semiconductor device includes a semiconductor chip having a plurality of electrodes formed on the surface thereof, and an interposer substrate on which the semiconductor chip is mounted. The interposer substrate has a core substrate, and built-up layers having more flexibility than the core substrate is built on only one surface of the core substrate, while the semiconductor chip is mounted on the other surface of the core substrate via an anisotropic conductive layer. The electrodes on the semiconductor chip and those provided on the core substrate are electrically connected via the anisotropic conductive layer, and the connection portions provided at the built-up layer is connected to predetermined patterns on a motherboard.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: April 13, 2004
    Assignee: Sony Corporation
    Inventors: Akira Yoshizawa, Tetsu Ishiyama, Yoshiyuki Nakamura
  • Publication number: 20020084522
    Abstract: A semiconductor formed by mounting a semiconductor chip on an interposer substrate and the manufacturing method therefor is disclosed. This semiconductor device includes a semiconductor chip having a plurality of electrodes formed on the surface thereof, and an interposer substrate on which the semiconductor chip is mounted. The interposer substrate has a core substrate, and built-up layers having more flexibility than the core substrate is built on only one surface of the core substrate, while the semiconductor chip is mounted on the other surface of the core substrate via an anisotropic conductive layer. The electrodes on the semiconductor chip and those provided on the core substrate are electrically connected via the anisotropic conductive layer, and the connection portions provided at the built-up layer is connected to predetermined patterns on a motherboard.
    Type: Application
    Filed: October 4, 2001
    Publication date: July 4, 2002
    Inventors: Akira Yoshizawa, Tetsu Ishiyama, Yoshiyuki Nakamura