Abstract: A semiconductor device includes: a plurality of first interconnections extending in a first direction and spaced from one another in a second direction crossing the first direction; a channel adjacent to the first interconnections in a third direction crossing the first direction and the second direction and extending in the second direction; and a plurality of first charge storage sections, each of the first charge storage sections provided between a corresponding one of the first interconnections and the channel. The first interconnections each include a first portion relatively farther from the channel and a second portion relatively closer to the channel, wherein the first portion includes a first thickness in the second direction and the second portion includes a second thickness in the second direction, and wherein the second thickness is substantially greater than the first thickness.

Abstract: A semiconductor device includes first conductive layers stacked in a first direction; a semiconductor film extending in the first direction; a first electrode film disposed between a corresponding one of the first conductive layers and the semiconductor film, and extending in a second direction; and a first insulating film disposed between the first conductive layer and the first electrode film. The first insulating film includes a first portion extending along a first sidewall of the first electrode film; a second portion that extends from an upper end of the first portion in a third direction to extend along an upper surface of the first electrode film; and a third portion that extends from a lower end of the first portion in the third direction to extend along a lower surface of the first electrode film.

Abstract: According to one embodiment, a semiconductor storage device includes a first interconnection, a second interconnection, a first channel part, a second channel part, a first charge storage part, a second charge storage part, a first insulator, a second insulator, and a third insulator. The first insulator includes a portion between at least a portion of the first charge storage part and at least a portion of the second charge storage part, and extends in a first direction. The second insulator is between the first insulator and the first interconnection, and extends in the first direction at a position arranged with respect to the first charge storage part in the first direction. The third insulator is between the second interconnection and the first insulator, and extends in the first direction at a position arranged with respect to the second charge storage part in the first direction.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of first interconnection layers, a semiconductor layer, a first charge storage part, a conductor, and a connection portion. The plurality of first interconnection layers extend in a first direction and are arrayed in a second direction intersecting the first direction. The semiconductor layer extends in the second direction and faces the plurality of first interconnection layers in a third direction intersecting the first direction and the second direction. The first charge storage part is provided between a first interconnection layer and the semiconductor layer. The conductor extends in the second direction on an opposite side of the first charge storage part with respect to the semiconductor layer. The connection portion has a first end that is in contact with the semiconductor layer and a second end that is in contact with the conductor.

Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a plurality of wiring layers stacked via a plurality of insulating layers above the substrate, the wiring layers having an opening extending in a direction perpendicular to the substrate, each of the wiring layers including a first face recessed in a first direction, a second face recessed in a second direction, third face recessed in a third direction, and a fourth face recessed in a fourth direction; a block insulating film provided to be in contact with each of the first to fourth faces; a charge storage film provided on a side face of the block insulating film; a tunnel insulating film provided on a side face of the charge storage film; and a semiconductor film provided on a side face of the tunnel insulating film.

Abstract: According to one embodiment, a semiconductor storage device includes a first interconnection, a second interconnection, a first channel part, a second channel part, a first charge storage part, a second charge storage part, a first insulator, a second insulator, and a third insulator. The first insulator includes a portion between at least a portion of the first charge storage part and at least a portion of the second charge storage part, and extends in a first direction. The second insulator is between the first insulator and the first interconnection, and extends in the first direction at a position arranged with respect to the first charge storage part in the first direction. The third insulator is between the second interconnection and the first insulator, and extends in the first direction at a position arranged with respect to the second charge storage part in the first direction.

Abstract: According to one embodiment, a semiconductor storage device includes a first charge storage part, a first insulating part, a second charge storage part, a second insulating part, a first select transistor, and a hollow part. The first charge storage part is at a first position separated from a surface of a substrate by a first distance in a third direction. The first select transistor is at a second position separated from the surface of the substrate by a second distance in the third direction. The second distance is greater than the first distance. The hollow part is up to a third position in the third direction separated from the surface of the substrate by a third distance in the third direction. The third distance is greater than or equal to the first distance and shorter than or equal to the second distance.

Abstract: A memory device includes a first conductive layer and a second conductive layer. A variable resistance layer is disposed between the first conductive layer and the second conductive layer and includes a first layer containing a semiconductor or a first metal oxide, and a second layer containing a second metal oxide. A phase-change layer is disposed either between the first conductive layer and the variable resistance layer or between the second conductive layer and the variable resistance layer.

Abstract: According to one embodiment, a semiconductor storage device includes a first charge storage part, a first insulating part, a second charge storage part, a second insulating part, a first select transistor, and a hollow part. The first charge storage part is at a first position separated from a surface of a substrate by a first distance in a third direction. The first select transistor is at a second position separated from the surface of the substrate by a second distance in the third direction. The second distance is greater than the first distance. The hollow part is up to a third position in the third direction separated from the surface of the substrate by a third distance in the third direction. The third distance is greater than or equal to the first distance and shorter than or equal to the second distance.

Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a plurality of wiring layers stacked via a plurality of insulating layers above the substrate, the wiring layers having an opening extending in a direction perpendicular to the substrate, each of the wiring layers including a first face recessed in a first direction, a second face recessed in a second direction, third face recessed in a third direction, and a fourth face recessed in a fourth direction; a block insulating film provided to be in contact with each of the first to fourth faces; a charge storage film provided on a side face of the block insulating film; a tunnel insulating film provided on a side face of the charge storage film; and a semiconductor film provided on a side face of the tunnel insulating film.

Abstract: A memory device includes a first stacked structure including a plurality of first conductive layers extending in a first direction and arrayed along a second direction intersecting with the first direction, a second stacked structure provided on the first stacked structure and including a plurality of second conductive layers extending in the first direction and arrayed along the second direction, an insulating layer provided between the first and second stacked structures, a third conductive layer provided in the first stacked structure and extending in the second direction, and a fourth conductive layer provided in the second stacked structure, extending in the second direction, and including one portion and another portion located more away from the insulating layer in the second direction than the one portion, a length of the one portion in the first direction being larger than a length of the another portion in the first direction.

Abstract: A storage device includes a substrate; a plurality of insulating layers extending in a first direction; a plurality of first conductive layers extending in the first direction, and stacked alternately with the plurality of insulating layers along a second direction that intersects the first direction and is perpendicular to the substrate; a second conductive layer extending in the second direction; a recording layer provided between the second conductive layer and the plurality of first conductive layers; a first transistor electrically connected to the second conductive layer; a second transistor provided adjacent to the first transistor in a third direction that intersects the first direction and the second direction and is parallel to the substrate; and a first insulator provided on the second transistor.

Abstract: A memory device includes first interconnects extending in a first direction; a second interconnect extending in a second direction crossing the first interconnects; an insulating film provided between two first interconnects; and a resistance change film between the first interconnects and the second interconnect. The resistance change film includes a first layer and second layers, the first layer extending in the second direction along the second interconnect, and the second layers being provided selectively between the respective first interconnects and the first layer. The second layers protrude toward the second interconnect exceeding an end surface of the insulating film in a third direction from the respective first interconnects toward the second interconnect. The respective second layers have a surface on a side of the first interconnects, and a width in the second direction of the surface is wider than a width in the second direction of the first interconnect.

Abstract: A memory device includes: a first conductive layer extending in a first direction, and a second conductive layer extending in a second direction intersecting with the first direction. A third conductive layer is electrically connected to the second conductive layer. A variable resistance layer includes a first layer containing a semiconductor or a first metal oxide and a second layer located between the first layer and the second conductive layer and containing a second metal oxide. The second layer includes a first end and a second end spaced from the third conductive layer farther than the first end. An intermediate layer is provided between the variable resistance layer and the second conductive layer and has a resistivity higher than that of the second layer. An insulator is provided between the first end and the second conductive layer and has a resistivity higher than that of the second layer.

Abstract: A memory device includes a first conductive layer and a second conductive layer. A variable resistance layer is disposed between the first conductive layer and the second conductive layer and includes a first layer containing a semiconductor or a first metal oxide, and a second layer containing a second metal oxide. A phase-change layer is disposed either between the first conductive layer and the variable resistance layer or between the second conductive layer and the variable resistance layer.

Abstract: A memory device includes first interconnects extending in a first direction; a second interconnect extending in a second direction crossing the first interconnects; an insulating film provided between two first interconnects; and a resistance change film between the first interconnects and the second interconnect. The resistance change film includes a first layer and second layers, the first layer extending in the second direction along the second interconnect, and the second layers being provided selectively between the respective first interconnects and the first layer. The second layers protrude toward the second interconnect exceeding an end surface of the insulating film in a third direction from the respective first interconnects toward the second interconnect. The respective second layers have a surface on a side of the first interconnects, and a width in the second direction of the surface is wider than a width in the second direction of the first interconnect.

Abstract: A memory device includes a first interconnection extending in a first direction; a second interconnection crossing the first interconnection and extending in a second direction; a resistance change film provided between the first interconnection and the second interconnection, and an intermediate film provided between the second interconnection and the resistance change film. The intermediate film is in contact with the second interconnection, and includes an insulating material.

Abstract: A thin film transistor includes semiconductor layer, source electrode, and drain electrode. The semiconductor layer includes first to fifth regions. The third region is provided between the first and second regions. The first region is disposed between the fourth and third regions. The second region is disposed between the fifth and third regions. The semiconductor layer includes an oxide. The source electrode is connected to the first region. The drain electrode is connected to the second region. First thickness of the first region along a second direction is thinner than third thickness along the second direction of each of the third to fifth regions. The second direction crosses a first direction and connects the first region and the source electrode. The first direction connects the first and second regions. Second thickness of the second region along the second direction is thinner than the third thickness.

Abstract: According to one embodiment, a solid-state imaging device includes a plurality of photoelectric conversion elements, a field effect transistor, a trench, and a P-type impurity diffusion region. The plurality of photoelectric conversion elements is two-dimensionally arranged in a semiconductor layer. The field effect transistor includes N-type source and drain on a surface side of the semiconductor layer. The trench penetrates through a surface and a rear surface of the semiconductor layer and surrounds each of the photoelectric conversion elements. The width of the trench is enlarged from the surface of the semiconductor layer toward a position at a predetermined depth, and is not enlarged at a position deeper than the position at the predetermined depth. The P-type impurity diffusion region is arranged in a side surface of the trench.

Abstract: A semiconductor device according to an embodiment includes a gate electrode, a first dielectric film, an oxide semiconductor film, a second dielectric film, a source electrode and a drain electrode. The first dielectric film is placed above the gate electrode. The oxide semiconductor film is placed above the first dielectric film. The oxide semiconductor film is formed to have a film thickness in a first contact region in contact with the source electrode and a second contact region in contact with the drain electrode larger than a film thickness in a channel region of the oxide semiconductor film so that a film portion of the first contact region projects toward the source electrode side and a film portion of the second contact region projects toward the drain electrode side.