Patents by Inventor Tetsu Nagamatsu

Tetsu Nagamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140078624
    Abstract: According to an embodiment, a semiconductor integrated circuit includes a first power supply terminal, a second power supply terminal, a regulator circuit, an electrostatic discharge (ESD) protection circuit, and a level shift circuit. A first voltage is applied to the first power supply terminal. A second voltage different from the first voltage is applied to the second power supply terminal. The regulator circuit adjusts the second voltage, and outputs the second voltage adjusted as an output voltage to an output terminal. The ESD protection circuit discharges ESD generated at the output terminal. The level shift circuit level-shifts the magnitude of the first voltage to the magnitude of the second voltage, and outputs a first control signal to electrically separate the regulator circuit from the ESD protection circuit depending on whether or not the first and second voltages are applied.
    Type: Application
    Filed: February 26, 2013
    Publication date: March 20, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: TETSU NAGAMATSU, KATSUYA KUDO
  • Patent number: 7576629
    Abstract: A semiconductor device according to the one embodiment of the present invention comprises a signal line; and a reference potential plane which is separated from the signal line and opposed to the signal line, the reference potential plane being provided with a discontinuous region in a portion intersecting with the signal line, as a delay element to be added to the signal line.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: August 18, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsu Nagamatsu, Yuuichi Hotta
  • Publication number: 20060146135
    Abstract: A semiconductor device according to the one embodiment of the present invention comprises a signal line; and a reference potential plane which is separated from the signal line and opposed to the signal line, the reference potential plane being provided with a discontinuous region in a portion intersecting with the signal line, as a delay element to be added to the signal line.
    Type: Application
    Filed: December 7, 2005
    Publication date: July 6, 2006
    Inventors: Tetsu Nagamatsu, Yuuichi Hotta
  • Patent number: 6011713
    Abstract: A semiconductor memory includes a memory cell including inverters (IN1, IN2), control transistors (T3, T4) that control the potential of a ground side terminal (N3) connected to the memory cell, and transfer transistors T1 and T2 that control transfer of data from bit lines (BL, /BL) to the memory cell. In writing data, the control transistors raise the potential of the ground side terminal (N3) to be higher than the ground potential by a predetermined potential. After the transfer transistors transfer data having a potential difference smaller than a potential difference between the power supply potential and the ground potential from the bit lines (BL, /BL) to the memory cell, and cause the memory cell to hold the data, the potential of the ground side terminal (N3) is decreased to the ground potential to write data.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: January 4, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumiyuki Yamane, Tadahiro Kuroda, Toshinari Takayanagi, Masataka Matsui, Yasuo Unekawa, Tetsu Nagamatsu
  • Patent number: 5959472
    Abstract: In the constant current drive type driver used for an LVDS (low voltage differential signal) interface, the parasitic capacitance of the package pins is charged and discharged sufficiently at a high speed to secure the high speed signal transmission operation. Further, the AC differential amplitude large enough to be received by the receiver can be obtained. The driver circuit device comprises: a transmit circuit composed of transistors (52, 53, 56, 57) for transmitting a signal by switching the signal current direction flowing through a pair of transmission lines (8, 9) connected between two output terminals (13 and 13B); and a constant current source composed of transistors (54, 75) for controlling the current value of the transmit circuit. In the idle state, only one of the two transistors (54 and 75) of the constant current source is turned on to limit the signal current flowing through the output terminals (13 and 13B).
    Type: Grant
    Filed: January 28, 1997
    Date of Patent: September 28, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsu Nagamatsu, Tadahiro Kuroda
  • Patent number: 5764086
    Abstract: The comparator circuit comprises a first comparator circuit having a differential input stage composed of P-channel FETs; a second comparator circuit having a differential input stage composed of N-channel FETs; pull-up and pull-down resistances connected to the output terminals of the two comparator circuits, respectively; at least one skew adjusting circuit having a delay circuit and a selector; and a logical gate for obtaining the two output signals of the two comparator circuits. Since the two differential input signals can be received by the two comparator circuits and according to the potentials of the two differential input signals, even if the supply potential is low, the comparator circuit can compare the two differential input signals in a wide potential range from the ground potential and the supply potential, so that it is possible to provide a high speed interface circuit which can satisfy the LVDS standard at a low supply potential.
    Type: Grant
    Filed: September 4, 1996
    Date of Patent: June 9, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsu Nagamatsu, Tadahiro Kuroda
  • Patent number: 5680127
    Abstract: A parallel-to-serial conversion device capable of improved space efficiency has a corner turn memory array provided in an input section of the device to perform parallel-to-serial conversion by writing in the row direction of the input section and by reading out in the column direction of the input section, write section for selectively writing data into a first pair of memory cells of said corner turn memory array; and readout section for simultaneously reading data from a second pair of memory cells which are different from the first pair of memory cells.
    Type: Grant
    Filed: February 9, 1995
    Date of Patent: October 21, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsu Nagamatsu, Masataka Matsui
  • Patent number: 5673214
    Abstract: Disclosed is an improved discrete cosine transform processor comprising an input unit for receiving image data to be processed, a storage unit for previously storing a result of a multiplication and accumulation calculation effected beforehand with respect to image input data and transform matrix components so that the same value is read from the same read line; a decoding unit for selecting the read line, in which each bit value of the image input data composed of a plurality of bits serves as a piece of address data; an accumulation unit for accumulating the data read from the storage unit and an output unit for outputting a result of the accumulation processing as output data. The storage unit uses the common data in common when effecting the multiplication and accumulation calculation, and, hence, a storage capacity is reduced, thereby making it possible to decrease a chip area.
    Type: Grant
    Filed: August 28, 1996
    Date of Patent: September 30, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Lee-Sup Kim, Tetsu Nagamatsu, Takayasu Sakurai
  • Patent number: 5629537
    Abstract: A semiconductor device has a plurality of basic cells fabricated on a single semiconductor substrate. Each of the basic cells comprises a first-conduction-type FETs, a second-conduction-type FETs, and a bipolar transistor. The collector region of the bipolar transistor is formed in a well region where the first-conduction-type FETs are formed. The bipolar transistor is formed between the first-conduction-type FETs of adjacent ones of the basic cells separated by an element insulation film.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: May 13, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsu Nagamatsu, Hiroshi Momose
  • Patent number: 5598361
    Abstract: A discrete cosine transform processor for executing discrete cosine transform calculations in both forward and inverse directions on the basis of previously stored product addition data has a memory having a first memory section for storing product addition calculation data for the forward direction transformation and a second memory section for storing product addition calculation data for the inverse direction transformation other than data in common to those stored in the first memory section; and sign inverter for inverting signs of the data used in common for the inverse direction transformation, among the data stored in the first memory section. The memory preferably includes first memory for storing product addition data corresponding to even-order coefficients and second memory for storing product addition data corresponding to odd-order coefficients; and only the second memory stores data used in common for both the forward and inverse direction transformations in the first memory thereof.
    Type: Grant
    Filed: October 26, 1994
    Date of Patent: January 28, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsu Nagamatsu, Lee-Sup Kim
  • Patent number: 5066996
    Abstract: A semiconductor device is disclosed having a channelless gate array. A plurality of standard cells are formed on a gate array chip such that one of the standard cells is formed relative to the adjacent standard cell with a bipolar transistor and resistor shared, as a BiCMOS logic gate, by the mutually adjacent standard cells at one end.
    Type: Grant
    Filed: April 15, 1991
    Date of Patent: November 19, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Hara, Yasuhiro Sugimoto, Tetsu Nagamatsu