Patents by Inventor Tetsu Negishi

Tetsu Negishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12136582
    Abstract: A power module is obtained in which the thermal resistance in the range from a semiconductor device to a base plate is reduced and the stress in the joining portion is relieved. The power module includes at least one semiconductor device, an insulating substrate having an insulating layer, a circuit layer provided on an upper surface of the insulating layer and a metal layer provided on a lower surface of the insulating layer, and a sintering joining member with an upper surface larger in outer circumference than a back surface of the at least one semiconductor device, to join together the back surface of the at least one semiconductor device and an upper surface of the circuit layer on an upper-surface side of the insulating layer.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: November 5, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoshinori Yokoyama, Tetsu Negishi, Koji Yamazaki
  • Publication number: 20240355874
    Abstract: A semiconductor apparatus includes: a semiconductor substrate; a first surface electrode on the substrate and a second surface electrode formed separately and insulated from the first surface electrode; an electroconductive layer formed between the electrodes with a space from the electrodes; an insulating layer formed to cover the electroconductive layer, a surface between the electrodes, and an end portion of each electrode on a side close to the electroconductive layer; a short-circuit prevention layer having an insulating property formed to cover the insulating layer between the electrodes and the electroconductive layer, the short-circuit prevention layer having a thickness equal to or larger than a height of the electroconductive layer and being made of a material different from that of the insulating layer; a metal plating layer formed on the electrodes; and a reverse-surface electrode on the opposite surface of the substrate, thereby being capable of preventing the electrodes from short-circuiting.
    Type: Application
    Filed: October 14, 2021
    Publication date: October 24, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Atsufumi INOUE, Tetsu NEGISHI, Tsuyoshi KAWAKAMI, Tomohiro TAMAKI
  • Publication number: 20240274557
    Abstract: A surface electrode on the front surface of a semiconductor element and a metal foil provided on the surface electrode are partially joined, which makes it possible to reduce stress generated at the end of the metal foil, prevent a failure resulting from a crack in the front surface of the semiconductor element, and enhance reliability of the semiconductor device. Such a semiconductor device includes a semiconductor element having a front surface and a back surface, a surface electrode formed on the front surface of the semiconductor element, and a metal foil partially joined onto an upper surface of the surface electrode.
    Type: Application
    Filed: June 14, 2021
    Publication date: August 15, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yo TANAKA, Tetsu NEGISHI, Seiji OKA
  • Publication number: 20220415747
    Abstract: A power module is obtained in which the thermal resistance in the range from a semiconductor device to a base plate is reduced and the stress in the joining portion is relieved. The power module includes at least one semiconductor device, an insulating substrate having an insulating layer, a circuit layer provided on an upper surface of the insulating layer and a metal layer provided on a lower surface of the insulating layer, and a sintering joining member with an upper surface larger in outer circumference than a back surface of the at least one semiconductor device, to join together the back surface of the at least one semiconductor device and an upper surface of the circuit layer on an upper-surface side of the insulating layer.
    Type: Application
    Filed: December 26, 2019
    Publication date: December 29, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yoshinori YOKOYAMA, Tetsu NEGISHI, Koji YAMAZAKI
  • Patent number: 11251161
    Abstract: An object of the present invention is to suppress reduction in a temperature cycle life of a wiring in a two-in-one type chopper module. A two-in-one type chopper module according to the present invention includes: a switching transistor; a first diode inverse-parallelly connected to the switching transistor; a second diode serially connected to the switching transistor and the first diode; a first wiring pattern mounting the switching transistor and the first diode; and a second wiring pattern mounting the second diode, wherein each of the switching transistor and the first diode has a power loss substantially identical with each other at a time of a forward direction current conduction, and an effective area of the second diode is larger than an effective area of the first diode.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: February 15, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeru Hasegawa, Tetsu Negishi
  • Patent number: 11145712
    Abstract: A semiconductor apparatus includes a power semiconductor device, a resin film and a sealing insulating material. The power semiconductor device includes: a first electrode covering a first region on one main surface of the semiconductor substrate; a second electrode formed on the other main surface of the semiconductor substrate; a guard ring formed in a second region outer than the first region; and a non-conductive inorganic film located in the second region and covering the guard ring. The resin film overlaps the guard ring in a plan view, and the resin film on the non-conductive inorganic film has a thickness of 35 ?m or more. The resin film is a film of a single layer, and the resin film has an outermost edge in the form of a downwardly spreading fillet. The outermost edge of the resin film is inner than an outermost edge of the semiconductor substrate.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: October 12, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tetsu Negishi, Shoichi Kuga
  • Patent number: 11063025
    Abstract: Gates of a plurality of semiconductor switching elements are electrically connected to a common gate control pattern by gate wires. Sources of the plurality of semiconductor switching elements are electrically connected to a common source control pattern by source wires. The gate control pattern is disposed to interpose the source control pattern between the gate control pattern and each of the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel. Hence, each of the gate wires becomes longer than each of the source wires, and has an inductance larger than the source wire. Accordingly, gate oscillation is reduced or suppressed in the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 13, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Junichi Nakashima, Shota Morisaki, Yoshiko Tamada, Yasushi Nakayama, Tetsu Negishi, Ryo Tsuda, Yukimasa Hayashida, Ryutaro Date
  • Publication number: 20200343226
    Abstract: An object of the present invention is to suppress reduction in a temperature cycle life of a wiring in a two-in-one type chopper module. A two-in-one type chopper module according to the present invention includes: a switching transistor; a first diode inverse-parallelly connected to the switching transistor; a second diode serially connected to the switching transistor and the first diode; a first wiring pattern mounting the switching transistor and the first diode; and a second wiring pattern mounting the second diode, wherein each of the switching transistor and the first diode has a power loss substantially identical with each other at a time of a forward direction current conduction, and an effective area of the second diode is larger than an effective area of the first diode.
    Type: Application
    Filed: September 28, 2017
    Publication date: October 29, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shigeru HASEGAWA, Tetsu NEGISHI
  • Publication number: 20200185359
    Abstract: Gates of a plurality of semiconductor switching elements are electrically connected to a common gate control pattern by gate wires. Sources of the plurality of semiconductor switching elements are electrically connected to a common source control pattern by source wires. The gate control pattern is disposed to interpose the source control pattern between the gate control pattern and each of the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel. Hence, each of the gate wires becomes longer than each of the source wires, and has an inductance larger than the source wire. Accordingly, gate oscillation is reduced or suppressed in the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel.
    Type: Application
    Filed: August 27, 2018
    Publication date: June 11, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Junichi NAKASHIMA, Shota MORISAKI, Yoshiko TAMADA, Yasushi NAKAYAMA, Tetsu NEGISHI, Ryo TSUDA, Yukimasa HAYASHIDA, Ryutaro DATE
  • Publication number: 20200058733
    Abstract: A semiconductor apparatus includes a power semiconductor device, a resin film and a sealing insulating material. The power semiconductor device includes: a first electrode covering a first region on one main surface of the semiconductor substrate; a second electrode formed on the other main surface of the semiconductor substrate; a guard ring formed in a second region outer than the first region; and a non-conductive inorganic film located in the second region and covering the guard ring. The resin film overlaps the guard ring in a plan view, and the resin film on the non-conductive inorganic film has a thickness of 35 ?m or more. The resin film is a film of a single layer, and the resin film has an outermost edge in the form of a downwardly spreading fillet. The outermost edge of the resin film is inner than an outermost edge of the semiconductor substrate.
    Type: Application
    Filed: April 24, 2017
    Publication date: February 20, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tetsu NEGISHI, Shoichi KUGA
  • Patent number: 10181445
    Abstract: A power module includes a power semiconductor element, an interconnection material, a circuit board, an external terminal, a joining material, and a sealing resin. A clearance portion is continuously formed between the sealing resin and each of an end surface of the joining material and a surface of the interconnection material so as to extend from the end surface of the joining material to the surface of the interconnection material, the end surface of the joining material being located between the power semiconductor element and the interconnection material, the surface of the interconnection material being located between the end surface and a predetermined position of the interconnection material separated by a distance from the end surface.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: January 15, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akihisa Fukumoto, Tetsu Negishi, Kei Yamamoto, Toshiaki Shinohara, Kazuyasu Nishikawa
  • Patent number: 10068825
    Abstract: A semiconductor device includes: a semiconductor element which includes semiconductor substrate, an insulating film formed on a front surface of the semiconductor substrate and having an opening, and an electrode formed in the opening on the front surface of the semiconductor substrate; and a first protective film disposed to cover the semiconductor element. The insulating film has a thickness of not less than 1/500 of a thickness of the semiconductor substrate and not more than 4 ?m. The insulating film has a compressive stress per film thickness of not less than 100 MPa/?m.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: September 4, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsu Negishi, Mamoru Terai, Kei Yamamoto
  • Publication number: 20170352629
    Abstract: A power module includes a power semiconductor element, an interconnection material, a circuit board, an external terminal, a joining material, and a sealing resin. A clearance portion is continuously formed between the sealing resin and each of an end surface of the joining material and a surface of the interconnection material so as to extend from the end surface of the joining material to the surface of the interconnection material, the end surface of the joining material being located between the power semiconductor element and the interconnection material, the surface of the interconnection material being located between the end surface and a predetermined position of the interconnection material separated by a distance from the end surface.
    Type: Application
    Filed: September 29, 2015
    Publication date: December 7, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Akihisa FUKUMOTO, Tetsu NEGISHI, Kei YAMAMOTO, Toshiaki SHINOHARA, Kazuyasu NISHIKAWA
  • Publication number: 20170033028
    Abstract: A semiconductor device includes: a semiconductor element which includes semiconductor substrate, an insulating film formed on a front surface of the semiconductor substrate and having an opening, and an electrode formed in the opening on the front surface of the semiconductor substrate; and a first protective film disposed to cover the semiconductor element. The insulating film has a thickness of not less than 1/500 of a thickness of the semiconductor substrate and not more than 4 ?m. The insulating film has a compressive stress per film thickness of not less than 100 MPa/?m.
    Type: Application
    Filed: March 17, 2015
    Publication date: February 2, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tetsu NEGISHI, Mamoru TERAI, Kei YAMAMOTO
  • Patent number: 9329433
    Abstract: A metal line 731 is formed in a linear area S of an insulative substrate 720, and moreover a metal line 732 is formed generally parallel to the metal line 731 with a specified distance thereto. The metal line 731 is connected to an n-type semiconductor core 701 of bar-like structure light-emitting elements 710A to 710D, and the metal line 732 is connected to a p-type semiconductor layer 702. By dividing the insulative substrate 720 into a plurality of divisional substrates, a plurality of light-emitting devices in each of which a plurality of bar-like structure light-emitting elements 710 are placed on the divisional substrates are formed.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: May 3, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsu Negishi, Akihide Shibata, Kenji Komiya, Fumiyoshi Yoshioka, Hiroshi Iwata, Akira Takahashi
  • Patent number: 9287242
    Abstract: In a light emitting device, one hundred or more bar-like structured light emitting elements (210) each having a light emitting area of 2,500? ?m2 or less are placed on a mounting surface of one insulating substrate (200), so that the light emitting device fulfills little variation in luminance, long life, and high efficiency by dispersion of light emission with suppression of increase in temperatures in light emitting operations.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: March 15, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Akihide Shibata, Tetsu Negishi, Kenji Komiya, Hiroshi Iwata, Akira Takahashi
  • Patent number: 9190590
    Abstract: A light-emitting element includes a first conductivity type semiconductor base, a plurality of first conductivity type protrusion-shaped semiconductors formed on the semiconductor base, and a second conductivity type semiconductor layer that covers the protrusion-shaped semiconductors.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: November 17, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Akihide Shibata, Tetsu Negishi, Kenji Komiya, Yoshifumi Yaoi, Takeshi Shiomi, Hiroshi Iwata, Akira Takahashi
  • Patent number: 9181630
    Abstract: This method for disposing fine objects, in a substrate preparing step, prepares a substrate having specified positions where fine objects (120) are to be disposed in an area where a first electrode (111) and a second electrode (112) face each other, and in a fluid introducing step, a fluid (121) is introduced on the substrate (110). The fluid (121) contains a plurality of the fine objects (120). The fine objects (120) are diode elements, each of which has, as an alignment structure, a front side layer (130) composed of a dielectric material, and a rear side layer (131) composed of a semiconductor. In the fine object disposing step, by applying an AC voltage to between the first electrode (111) and the second electrode (112), the fine objects (120) are disposed by dielectrophoresis with the front side layer (130) facing up at the predetermined positions in the area (A) where the first electrode (111) and the second electrode (112) face each other.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: November 10, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akihide Shibata, Tetsu Negishi, Kenji Komiya, Yoshifumi Yaoi, Takeshi Shiomi, Hiroshi Iwata, Akira Takahashi
  • Patent number: 8872214
    Abstract: To facilitate electrode connections and achieve a high light emitting efficiency, a rod-like light-emitting device includes a semiconductor core of a first conductivity type having a rod shape, and a semiconductor layer of a second conductivity type formed to cover the semiconductor core. The outer peripheral surface of part of the semiconductor core is exposed.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: October 28, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsu Negishi, Akihide Shibata, Satoshi Morishita, Kenji Komiya, Hiroshi Iwata, Akira Takahashi
  • Publication number: 20130221385
    Abstract: A light-emitting element includes a first conductivity type semiconductor base, a plurality of first conductivity type protrusion-shaped semiconductors formed on the semiconductor base, and a second conductivity type semiconductor layer that covers the protrusion-shaped semiconductors.
    Type: Application
    Filed: June 22, 2011
    Publication date: August 29, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Akihide Shibata, Tetsu Negishi, Kenji Komiya, Yoshifumi Yaoi, Takeshi Shiomi, Hiroshi Iwata, Akira Takahashi