Patents by Inventor Tetsu Udagawa
Tetsu Udagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6924525Abstract: The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL1, BL2 are, respectively, 2 ?/? or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL1, BL2 by which the number of the steps of manufacturing the DRAM can be reduced.Type: GrantFiled: August 19, 2003Date of Patent: August 2, 2005Assignee: Hitachi, Ltd.Inventors: Seiji Narui, Tetsu Udagawa, Kazuhiko Kajigaya, Makoto Yoshida
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Publication number: 20040031980Abstract: The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL1, BL2 are, respectively, 2 &OHgr;/□ or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL1, BL2 by which the number of the steps of manufacturing the DRAM can be reduced.Type: ApplicationFiled: August 19, 2003Publication date: February 19, 2004Inventors: Seiji Narui, Tetsu Udagawa, Kazuhiko Kajigaya, Makoto Yoshida
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Patent number: 6635918Abstract: The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL1, BL2 are, respectively, 2 &OHgr;/□ or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL1, BL2 by which the number of the steps of manufacturing the DRAM can be reduced.Type: GrantFiled: November 17, 2000Date of Patent: October 21, 2003Assignee: Hitachi, Ltd.Inventors: Seiji Narui, Tetsu Udagawa, Kazuhiko Kajigaya, Makoto Yoshida
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Patent number: 6150689Abstract: The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q of a DRAM and a sheet resistance of bit lines BL.sub.1, BL.sub.2 are, respectively, 2 .OMEGA./.quadrature. or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL.sub.1, BL.sub.2 by which the number of the steps of manufacturing the DRAM can be reduced.Type: GrantFiled: January 13, 1997Date of Patent: November 21, 2000Assignee: Hitachi, Ltd.Inventors: Seiji Narui, Tetsu Udagawa, Kazuhiko Kajigaya, Makoto Yoshida
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Patent number: 6108264Abstract: An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or, in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.Type: GrantFiled: January 19, 1999Date of Patent: August 22, 2000Assignee: Hitachi, Ltd.Inventors: Yasushi Takahashi, Takashi Shinoda, Masamichi Ishihara, Tetsu Udagawa, Kazumasa Yanagisawa
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Patent number: 5862095Abstract: An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.Type: GrantFiled: October 31, 1997Date of Patent: January 19, 1999Assignee: Hitachi, Ltd.Inventors: Yasushi Takahashi, Takashi Shinoda, Masamichi Ishihara, Tetsu Udagawa, Kazumasa Yanagisawa
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Patent number: 5719815Abstract: An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or, in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.Type: GrantFiled: July 18, 1995Date of Patent: February 17, 1998Assignee: Hitachi, Ltd.Inventors: Yasushi Takahashi, Takashi Shinoda, Masamichi Ishihara, Tetsu Udagawa, Kazumasa Yanagisawa
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Patent number: 5701031Abstract: A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.Type: GrantFiled: July 25, 1994Date of Patent: December 23, 1997Assignee: Hitachi, Ltd.Inventors: Satoshi Oguchi, Masamichi Ishihara, Kazuya Ito, Gen Murakami, Ichiro Anjoh, Toshiyuki Sakuta, Yasunori Yamaguchi, Yasuhiro Kasama, Tetsu Udagawa, Eiji Miyamoto, Youichi Matsuno, Hiroshi Satoh, Atsusi Nozoe
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Patent number: 5506804Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.Type: GrantFiled: November 30, 1993Date of Patent: April 9, 1996Assignees: Hitachi, Ltd., VLSI Engineering Corp.Inventors: Kazumasa Yanagisawa, Tatsuyuki Ohta, Tetsu Udagawa, Kyoko Ishii, Hitoshi Miwa, Atsushi Nozoe, Masayuki Nakamura, Tetsurou Matsumoto, Yoshitaka Kinoshita, Yoshiaki Ouchi, Hiromi Tsukada, Shoji Wada, Kazuo Mihashi, Yutaka Kobayashi, Goro Kitsukawa
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Patent number: 5426616Abstract: A voltage conversion circuit of the present invention is equipped with means for generating a first voltage stabilized with respect to ground potential of a semiconductor integrated circuit device including the circuit, means for generating second voltage stabilized with respect to an external supply voltage of the semiconductor integrated circuit device, and selection means for selecting either the first voltage or the second voltage. The first voltage age, stabilized with respect to the ground potential, is selected and used as the voltage at the time of normal operation, and the second voltage, stabilized with respect to the external supply voltage, is selected and used at the time of aging test. In this case, means for trimming the first voltage and/or the second voltage is, preferably, provided to raise the voltage accuracy.Type: GrantFiled: May 16, 1994Date of Patent: June 20, 1995Assignee: Hitachi, Ltd.Inventors: Kazuhiko Kajigaya, Tetsu Udagawa, Kyoko Ishii, Manabu Tsunozaki, Kazuyoshi Oshima, Masashi Horiguchi, Jun Etoh, Masakazu Aoki, Shin'ichi Ikenaga, Kiyoo Itoh
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Patent number: 5332922Abstract: A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Each chip is bonded with an associated lead frame and each lead frame is disposed as plural lead frame conductors contacting mutually lead frame conductors associated with similarly function bonding pads, i.e. external terminals of the chips, of the other one of the pair of chips. Ones or plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal.Type: GrantFiled: April 26, 1991Date of Patent: July 26, 1994Assignee: Hitachi, Ltd.Inventors: Satoshi Oguchi, Masamichi Ishihara, Kazuya Ito, Gen Murakami, Ichiro Anjoh, Toshiyuki Sakuta, Yasunori Yamaguchi, Yasuhiro Kasama, Tetsu Udagawa, Eiji Miyamoto, Youichi Matsuno, Hiroshi Satoh, Atsusi Nozoe
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Patent number: 5276648Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.Type: GrantFiled: January 8, 1992Date of Patent: January 4, 1994Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kazumasa Yanagisawa, Tatsuyuki Ohta, Tetsu Udagawa, Kyoko Ishii, Hitoshi Miwa, Atsushi Nozoe, Masayuki Nakamura, Tetsurou Matsumoto, Yoshitaka Kinoshita, Yoshiaki Ouchi, Hiromi Tsukada, Shoji Wada, Kazuo Mihashi, Yutaka Kobayashi, Goro Kitsukawa
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Patent number: 5150325Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as curent signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.Type: GrantFiled: March 20, 1990Date of Patent: September 22, 1992Assignees: Hitachi, Ltd., Hitachi VLSI Engineering CorpInventors: Kazumasa Yanagisawa, Tatsuyuki Ohta, Tetsu Udagawa, Kyoko Ishii, Hitoshi Miwa, Atsushi Nozoe, Masayuki Nakamura, Tetsurou Matsumoto, Yoshitaka Kinoshita, Yoshiaki Ouchi, Hiromi Tsukada, Shoji Wada, Kazuo Mihashi, Yutaka Kobayashi, Goro Kitsukawa
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Patent number: 5043947Abstract: A memory device is provided including a plurality of memory arrays and peripheral circuits. For example, in a dynamic RAM the peripheral circuitry will include row address decoders, column address decoders, sense amplifiers and main amplifiers disposed in such a manner as to correspond to the memory arrays, respectively. The desired row address decoders, column address decoders, sense amplifiers and main amplifiers are selectively operated in accordance with a common array selection signal generated on the basis of at least part of row address signals. Accordingly, only the row address decoders, column address decoders, sense amplifiers and main amplifiers corresponding to the memory array containing the designated memory cells are operated selectively in accordance with the common array selection signal. It is thus possible to reduce power consumption of the dynamic RAM and to simplify the structure of the peripheral circuits and wirings.Type: GrantFiled: May 30, 1990Date of Patent: August 27, 1991Assignee: Hitachi, Ltd.Inventors: Kazuyoshi Oshima, Takashi Yamazaki, Yasuhiro Kasama, Tetsu Udagawa, Hiroaki Kotani
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Patent number: 4941129Abstract: A memory device is provided including a plurality of memory arrays and peripheral circuits. For example, in a dynamic RAM the peripheral circuitry will include row address decoders, column address decoders, sense amplifiers and main amplifiers disposed in such a manner as to correspond to the memory arrays, respectively. The desired row address decoders, column address decoders, sense amplifiers and main amplifiers are selectively operated in accordance with a common array selection signal generated on the basis of at least part of row address signals. Accordingly, only the row address decoders, column address decoders, sense amplifiers and main amplifiers corresponding to the memory array containing the designated memory cells are operated selectively in accordance with the common array selection signal. It is thus possible to reduce power consumption of the dynamic RAM and to simplify the structure of the peripheral circuits and wirings.Type: GrantFiled: August 29, 1988Date of Patent: July 10, 1990Assignee: Hitachi, Ltd.Inventors: Kazuyoshi Oshima, Takashi Yamazaki, Yasuhiro Kasama, Tetsu Udagawa, Hiroaki Kotani
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Patent number: RE37539Abstract: A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.Type: GrantFiled: December 23, 1999Date of Patent: February 5, 2002Assignee: Hitachi, Ltd.Inventors: Satoshi Oguchi, Masamichi Ishihara, Kazuya Ito, Gen Murakami, Ichiro Anjoh, Toshiyuki Sakuta, Yasunori Yamaguchi, Yasuhiro Kasama, Tetsu Udagawa, Eiji Momose, Youichi Matsuno, Hiroshi Satoh, Atsusi Nozoe