Patents by Inventor Tetsuaki Murohashi

Tetsuaki Murohashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11899324
    Abstract: An electro-optical device includes a substrate, a scanning line provided between a first TFT and a second TFT, common wiring, a pixel electrode, a third relay electrode including a projecting portion overlapping the scanning line in plan view and protruding from the scanning line and electrically coupling the first TFT and the pixel electrode, a capacitance element provided between the substrate and the scanning line and overlapping the second TFT in plan view, and a second relay electrode including a projecting portion overlapping the scanning line in plan view and protruding from the scanning line and electrically coupling the capacitance element and the common wiring. A contact hole electrically coupling the pixel electrode and the third relay electrode overlaps a contact hole electrically coupling the capacitance element and the second relay electrode in plan view.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: February 13, 2024
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Tetsuaki Murohashi, Kikuya Morita
  • Patent number: 11860496
    Abstract: A liquid crystal apparatus includes a substrate, a pixel electrode, common wiring, a TFT provided between the substrate and the common wiring, a scanning line provided between the substrate and the TFT along a first direction, a capacitance element provided between the substrate and the scanning line and overlapping the scanning line in plan view, and a second relay electrode electrically coupled to the common wiring and overlapping the scanning line in plan view. The second relay electrode and a first capacitance electrode serving as one electrode of the capacitance element are electrically coupled to each other through a contact hole overlapping the scanning line and the first capacitance electrode in plan view. The scanning line has a cutout portion provided between the second relay electrode and the first capacitance electrode and surrounding at least three directions of the circumference of the contact hole.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: January 2, 2024
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Tetsuaki Murohashi, Kikuya Morita
  • Publication number: 20230328210
    Abstract: A liquid crystal apparatus includes a substrate, a pixel electrode, common wiring provided between the substrate and the pixel electrode, a TFT, a scanning line, a capacitance element provided between the substrate and the scanning line and overlapping the scanning line in plan view, and a second relay electrode electrically coupled to the common wiring and overlapping the scanning line in plan view. A first capacitance electrode serving as one electrode of the capacitance element includes a projecting portion protruding from the scanning line in plan view. The second relay electrode includes a projecting portion overlapping the projecting portion in plan view. The second relay electrode and the first capacitance electrode of the capacitance element are electrically coupled to each other through a contact hole provided between the projecting portion and the projecting portion.
    Type: Application
    Filed: March 27, 2023
    Publication date: October 12, 2023
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Tetsuaki Murohashi, Kikuya Morita, Yohei Sugimoto
  • Publication number: 20230305346
    Abstract: An electro-optical device includes a substrate, a scanning line provided between a first TFT and a second TFT, common wiring, a pixel electrode, a third relay electrode including a projecting portion overlapping the scanning line in plan view and protruding from the scanning line and electrically coupling the first TFT and the pixel electrode, a capacitance element provided between the substrate and the scanning line and overlapping the second TFT in plan view, and a second relay electrode including a projecting portion overlapping the scanning line in plan view and protruding from the scanning line and electrically coupling the capacitance element and the common wiring. A contact hole electrically coupling the pixel electrode and the third relay electrode overlaps a contact hole electrically coupling the capacitance element and the second relay electrode in plan view.
    Type: Application
    Filed: March 28, 2023
    Publication date: September 28, 2023
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Tetsuaki MUROHASHI, Kikuya MORITA
  • Publication number: 20230305348
    Abstract: A liquid crystal apparatus includes a substrate, a pixel electrode, common wiring, a TFT provided between the substrate and the common wiring, a scanning line provided between the substrate and the TFT along a first direction, a capacitance element provided between the substrate and the scanning line and overlapping the scanning line in plan view, and a second relay electrode electrically coupled to the common wiring and overlapping the scanning line in plan view. The second relay electrode and a first capacitance electrode serving as one electrode of the capacitance element are electrically coupled to each other through a contact hole overlapping the scanning line and the first capacitance electrode in plan view. The scanning line has a cutout portion provided between the second relay electrode and the first capacitance electrode and surrounding at least three directions of the circumference of the contact hole.
    Type: Application
    Filed: March 28, 2023
    Publication date: September 28, 2023
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Tetsuaki MUROHASHI, Kikuya MORITA
  • Patent number: 6340434
    Abstract: A method for chemical-mechanical polishing of a layer that is deposited on a surface of an integrated circuit substrate is described. The method includes: (1) immobilizing the integrated circuit substrate using a substrate holder such that the integrated circuit substrate surface is positioned against a surface of a polishing pad, which is mounted on a supporting surface; (2) a first stage of polishing the substrate surface including maintaining a predetermined difference between the rotational velocity of the polishing pad and the rotational velocity of the substrate holder allowing an endpoint of the chemical-mechanical polishing process of the layer to be detected; and (3) a second stage of polishing the substrate such that the rotational velocity of the polishing pad and the rotational velocity of the substrate holder are substantially the same to produce a substantially planar substrate surface.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: January 22, 2002
    Assignee: LSI Logic Corporation
    Inventors: Hiroshi Mizuno, Osamu Kinoshita, Tetsuaki Murohashi, Akihisa Ueno, Yoshifumi Sakuma, Kostas Amberiadis