Patents by Inventor Tetsuaki Nakamikawa
Tetsuaki Nakamikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8422830Abstract: An image processing system includes a first image processor that reads out a first image written in a main memory to apply a first process to the first image and write in the main memory as a second image, a second image processor that reads out a second image written in the main memory to apply a second process to the second image and write in the main memory as a second image, and an address snooping apparatus that snoops an address of the image written in the main memory to start the first process when the address is indicated to a previously set first value and start the second process when the address is indicated to a previously set second value, effectively enabling synchronization between a process by a CPU or a special purpose processor and a data delivery/receipt process between pipeline stages.Type: GrantFiled: January 10, 2008Date of Patent: April 16, 2013Assignee: Hitachi, Ltd.Inventors: Tetsuaki Nakamikawa, Shoji Muramatsu
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Patent number: 7941567Abstract: A modular computer system formed by connecting a processing module having a processor mounted thereon and a plurality of I/O modules in a stacked form via connectors, where differing ones of the plurality of I/O modules being differing types of I/O modules from one another, which operate with mutually differing types of bus-layout configurations. In accordance with the association of I/O modules with identification information, for each differing type of I/O module stacked via the connectors, said processing module selects from differing preset bus-layout configurations and device drivers from a memory, to dynamically reconfigure the reconfigurable generic bus for accessing the differing type of I/O module.Type: GrantFiled: July 24, 2007Date of Patent: May 10, 2011Assignee: Hitachi, Ltd.Inventors: Tsutomu Yamada, Tetsuaki Nakamikawa, Hiromichi Endoh, Noritaka Matsumoto, Hirokazu Kasashima
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Publication number: 20100088493Abstract: A restriction is given to the calculation function for image processing achieved by the hard-wired system and the memory access control of a buffer memory, and a range of the restriction is made variable by a program control and others. Data is inputted to the buffer memory from the outside with a restriction of “in units of memory line”, and the number of memory lines and positions of the same to which data is inputted can be programmable by the control circuit. The arithmetic circuit is subjected to the restriction of performing the calculation in units of data of one or plural memory lines supplied from the buffer memory, and a calculation processing content in units of calculation processing for the units of data can be programmably assigned by the control circuit.Type: ApplicationFiled: September 24, 2009Publication date: April 8, 2010Inventors: Yoshitaka TAKAHASHI, Shoji MURAMATSU, Tetsuaki NAKAMIKAWA, Hiroyuki HAMASAKI, So OTSUKA
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Patent number: 7558483Abstract: The system includes optical bus-bridging devices for observing the modes of said electric buses and the modes of said optical fibers while said electric buses have not been driven (OFF mode), so that the modes of the two electric buses connected through optical fibers are brought into agreement and that the buses can be simultaneously driven by a plurality of nodes. While one or both of said electric buses have been driven (ON mode) by the nodes connected thereto, an optical output has been continuously produced from the buses that are being driven to said optical fibers, and while light has been inputted from said optical fibers, the modes of said buses are not observed, but an electric output is produced to the electric bus of the side to which light is inputted to drive the bus. The optical bus-bridging device changes the mode of the electric bus when the optical fiber does not change within a predetermined period of time after the optical bus-bridging device has outputted a signal to the optical fiber.Type: GrantFiled: July 23, 2004Date of Patent: July 7, 2009Assignee: Hitachi, Ltd.Inventors: Hiroshi Arita, Tetsuaki Nakamikawa, Kenichi Kurosawa, Hiroaki Fukumaru, Hisao Ogawa
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Publication number: 20080170809Abstract: An image processing system includes a first image processor that reads out a first image written in a main memory to apply a first process to the first image and write in the main memory as a second image, a second image processor that reads out a second image written in the main memory to apply a second process to the second image and write in the main memory as a second image, and an address snooping apparatus that snoops an address of the image written in the main memory to start the first process when the address is indicated to a previously set first value and start the second process when the address is indicated to a previously set second value, effectively enabling synchronization between a process by a CPU or a special purpose processor and a data delivery/receipt process between pipeline stages.Type: ApplicationFiled: January 10, 2008Publication date: July 17, 2008Inventors: Tetsuaki Nakamikawa, Shoji Muramatsu
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Publication number: 20070266184Abstract: A modular computer system formed by connecting a processing module having a processor mounted thereon and a plurality of I/O modules in a stacked form via connectors, where differing ones of the plurality of I/O modules being differing types of I/O modules from one another, which operate with mutually differing types of bus-layout configurations. In accordance with the association of I/O modules with identification information, for each differing type of I/O module stacked via the connectors, said processing module selects from differing preset bus-layout configurations and device drivers from a memory, to dynamically reconfigure the reconfigurable generic bus for accessing the differing type of I/O module.Type: ApplicationFiled: July 24, 2007Publication date: November 15, 2007Inventors: Tsutomu YAMADA, Tetsuaki Nakamikawa, Hiromichi Endoh, Noritaka Matsumoto, Hirokazu Kasashima
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Patent number: 7272665Abstract: Without being restrained to a specific bus scheme, kinds of I/O modules connected to a processing module can be discriminated. Module exclusive selection parts respectively provided in I/O modules connected in a stacked form to a processing module via connectors judge only a module select signal input from terminals in the same position on processing module side connectors to be active. Based thereon, identification information of its own I/O module is output to a predetermined terminal on the connector. Without being restrained to a specific bus scheme, therefore, the processing module can acquire identification information of the I/O modules from a predetermined terminal on a connector. One I/O module can be selected by a simple module selection circuit scheme of inputting module select signals successively output from the processing module to terminals in the same position on processing module side connectors according to the connection order of the I/O modules.Type: GrantFiled: January 20, 2004Date of Patent: September 18, 2007Assignee: Hitachi, Ltd.Inventors: Tsutomu Yamada, Tetsuaki Nakamikawa, Hiromichi Endoh, Noritaka Matsumoto, Hirokazu Kasashima
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Publication number: 20040268011Abstract: The system includes optical bus-bridging devices for observing the modes of said electric buses and the modes of said optical fibers while said electric buses have not been driven (OFF mode), so that the modes of the two electric buses connected through optical fibers are brought into agreement and that the buses can be simultaneously driven by a plurality of nodes. While one or both of said electric buses have been driven (ON mode) by the nodes connected thereto, an optical output has been continuously produced from the buses that are being driven to said optical fibers, and while light has been inputted from said optical fibers, the modes of said buses are not observed, but an electric output is produced to the electric bus of the side to which light is inputted to drive the bus. The optical bus-bridging device changes the mode of the electric bus when the optical fiber does not change within a predetermined period of time after the optical bus-bridging device has outputted a signal to the optical fiber.Type: ApplicationFiled: July 23, 2004Publication date: December 30, 2004Inventors: Hiroshi Arita, Tetsuaki Nakamikawa, Kenichi Kurosawa, Hiroaki Fukumaru, Hisao Ogawa
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Publication number: 20040215841Abstract: Without being restrained to a specific bus scheme, kinds of I/O modules connected to a processing module can be discriminated. Module exclusive selection parts respectively provided in I/O modules connected in a stacked form to a processing module via connectors judge only a module select signal input from terminals in the same position on processing module side connectors to be active. Based thereon, identification information of its own I/O module is output to a predetermined terminal on the connector. Without being restrained to a specific bus scheme, therefore, the processing module can acquire identification information of the I/O modules from a predetermined terminal on a connector. One I/O module can be selected by a simple module selection circuit scheme of inputting module select signals successively output from the processing module to terminals in the same position on processing module side connectors according to the connection order of the I/O modules.Type: ApplicationFiled: January 20, 2004Publication date: October 28, 2004Inventors: Tsutomu Yamada, Tetsuaki Nakamikawa, Hiromichi Endoh, Noritaka Matsumoto, Hirokazu Kasashima
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Patent number: 6782202Abstract: The system includes optical bus-bridging devices for observing the modes of said electric buses and the modes of said optical fibers while said electric buses have not been driven (OFF mode), so that the modes of the two electric buses connected through optical fibers are brought into agreement and that the buses can be simultaneously driven by a plurality of nodes. While one or both of said electric buses have been driven (ON mode) by the nodes connected thereto, an optical output has been continuously produced from the buses that are being driven to said optical fibers, and while light has been inputted from said optical fibers, the modes of said buses are not observed, but an electric output is produced to the electric bus of the side to which light is inputted to drive the bus. The optical bus-bridging device changes the mode of the electric bus when the optical fiber does not change within a predetermined period of time after the optical bus-bridging device has outputted a signal to the optical fiber.Type: GrantFiled: May 29, 2001Date of Patent: August 24, 2004Assignee: Hitachi, Ltd.Inventors: Hiroshi Arita, Tetsuaki Nakamikawa, Kenichi Kurosawa, Hiroaki Fukumaru, Hisao Ogawa
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Patent number: 6631447Abstract: To provide a large scale multiprocessor system capable of executing an area limited cache coherency control implementing a high speed operation while substantially reducing the amount of processor-to-processor communications there is provided a translation lookaside buffer which retains cache coherency attribute information defining a limitable cache coherent area to maintain data consistency among caches, and a processor memory interface unit includes a cache coherency control which identifies whether cache coherency is required only within a particular cluster of processors or is required for every one of the cache memories in every one of the clusters throughout the system, on the basis of the contents of the cache coherency attribute information. Further, in another version of large scale multiprocessor system, each cluster may be provided with an export directory which registers an identifier of data whose copy is cached in cache memories in other clusters.Type: GrantFiled: March 26, 1997Date of Patent: October 7, 2003Assignee: Hitachi, Ltd.Inventors: Michio Morioka, Kenichi Kurosawa, Tetsuaki Nakamikawa, Sakoh Ishikawa
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Patent number: 6453391Abstract: A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which effect the same operation in synchronism with each other.Type: GrantFiled: June 18, 2001Date of Patent: September 17, 2002Assignee: Hitachi, Ltd.Inventors: Yuuichiro Morita, Tetsuaki Nakamikawa, Shinichiro Yamaguchi, Naoto Miyazaki, Shin Kokura, Yoshihiro Miyazaki
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Publication number: 20020120884Abstract: The present invention provides a multi-computer fault detection system comprising a plurality of computers in communication with each other, the computers comprising, a processor, a plurality of operating systems executed by the processor and a main memory for storing a task executed on one of the operating systems wherein the monitoring is whether a fault has occurred in another one of the operating systems wherein at least one of the computers with the fault alerts another one of the computers.Type: ApplicationFiled: August 14, 2001Publication date: August 29, 2002Inventors: Tetsuaki Nakamikawa, Masahiko Saito, Takanori Yokoyama, Hiroshi Ohno
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Publication number: 20020073411Abstract: A controller to which a plurality of apparatus can be connected has an apparatus discriminating unit for discriminating a type and/or the number of the apparatus connected to the controller. The controller further has an application discriminating unit for discriminating, based on the type and/or the number of the apparatuses discriminated by the apparatus discriminating unit, an application corresponding to the type and/or the number of the apparatuses.Type: ApplicationFiled: February 26, 2001Publication date: June 13, 2002Inventors: Kunihiko Tsunedomi, Shoji Suzuki, Tsutomu Yamada, Takanori Yokoyama, Masahiko Saito, Hidemitsu Naya, Satoru Funaki, Hiroshi Arita, Yoshinori Ohkura, Tetsuaki Nakamikawa
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Publication number: 20010032301Abstract: A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which effect a same operation in synchronism with each other.Type: ApplicationFiled: June 18, 2001Publication date: October 18, 2001Applicant: Hitachi, Ltd.Inventors: Yuuichiro Morita, Tetsuaki Nakamikawa, Shinichiro Yamaguchi, Naoto Miyazaki, Shin Kokura, Yoshihiro Miyazaki
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Publication number: 20010028487Abstract: The system includes optical bus-bridging devices for observing the modes of said electric buses and the modes of said optical fibers while said electric buses have not been driven (OFF mode), so that the modes of the two electric buses connected through optical fibers are brought into agreement and that the buses can be simultaneously driven by a plurality of nodes. While one or both of said electric buses have been driven (ON mode) by the nodes connected thereto, an optical output has been continuously produced from the buses that are being driven to said optical fibers, and while light has been inputted from said optical fibers, the modes of said buses are not observed, but an electric output is produced to the electric bus of the side to which light is inputted to drive the bus. The optical bus-bridging device changes the mode of the electric bus when the optical fiber does not change within a predetermined period of time after the optical bus-bridging device has outputted a signal to the optical fiber.Type: ApplicationFiled: May 29, 2001Publication date: October 11, 2001Applicant: Hitachi, Ltd.Inventors: Hiroshi Arita, Tetsuaki Nakamikawa, Kenichi Kurosawa, Hiroaki Fukumaru, Hisao Ogawa
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Patent number: 6249363Abstract: The system includes optical bus-bridging devices for observing the modes of said electric buses and the modes of said optical fibers while said electric buses have not been driven (OFF mode), so that the modes of the two electric buses connected through optical fibers are brought into agreement and that the buses can be simultaneously driven by a plurality of nodes. While one or both of said electric buses have been driven (ON mode) by the nodes connected thereto, an optical output has been continuously produced from the buses that are being driven to said optical fibers, and while light has been inputted from said optical fibers, the modes of said buses are not observed, but an electric output is produced to the electric bus of the side to which light is inputted to drive the bus. The optical bus-bridging device changes the mode of the electric bus when the optical fiber does not change within a predetermined period of time after the optical bus-bridging device has outputted a signal to the optical fiber.Type: GrantFiled: July 15, 1998Date of Patent: June 19, 2001Assignee: Hitachi, Ltd.Inventors: Hiroshi Arita, Tetsuaki Nakamikawa, Kenichi Kurosawa, Hiroaki Fukumaru, Hisao Ogawa
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Patent number: 6003116Abstract: A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which carry out the same operation in synchronism with each other.Type: GrantFiled: October 29, 1996Date of Patent: December 14, 1999Assignee: Hitachi, Ltd.Inventors: Yuuichiro Morita, Tetsuaki Nakamikawa, Shinichiro Yamaguchi, Naoto Miyazaki, Shin Kokura, Yoshihiro Miyazaki
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Patent number: 5956263Abstract: A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.Type: GrantFiled: January 31, 1997Date of Patent: September 21, 1999Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Masahisa Narita, Hisashi Kaziwara, Takeshi Asai, Shigeki Morinaga, Hiroyuki Kida, Mitsuru Watabe, Tetsuaki Nakamikawa, Shunpei Kawasaki, Junichi Tatezaki, Norio Nakagawa, Yugo Kashiwagi
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Patent number: 5841963Abstract: A dual computer system consisting of two computer systems connected by a plurality of data transfer units and a plurality of data transfer channels for a memory copy made to again synchronize both the computer systems at the time of recovery from a fault. When no fault occurs on the data transfer channels, the data transfer units share the load of data transfer in the memory copy operation, and when a fault occurs on any data transfer unit during the memory copy operation, the remaining normal data transfer units are used to again transfer data, whereby a memory copy is made at high speed for again synchronizing both the computer systems at the time of recovery from a fault, and system reliability at the time of recovery from a fault is improved.Type: GrantFiled: May 21, 1997Date of Patent: November 24, 1998Assignee: Hitachi, Ltd.Inventors: Tetsuaki Nakamikawa, Shin Kokura, Kenichi Kurosawa, Shinichiro Yamaguchi, Yoshihiro Miyazaki, Hiroshi Ohguro