Patents by Inventor Tetsufumi Kawamura

Tetsufumi Kawamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10605824
    Abstract: For the purpose of shortening the MEMS manufacturing TAT, the MEMS manufacturing method according to the present invention includes a step of extracting the first MEMS with first characteristic in a range approximate to the required characteristic from the plurality of MEMS preliminarily prepared on the main surface of the substrate, and a step of forming a second MEMS having the required characteristic by directly processing the first MEMS.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: March 31, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Shuntaro Machida, Nobuyuki Sugii, Keiji Watanabe, Daisuke Ryuzaki, Tetsufumi Kawamura, Kazuki Watanabe
  • Publication number: 20200033390
    Abstract: One preferable aspect of the present invention is a state detecting system which detects a state of a machine device based on a detection signal from a detecting element provided to the machine device, and is the state detecting system which includes a non-normal time rate detecting unit which detects a rate or a value as a non-normal time rate, the rate being a rate of an integration value of a time during which an amplitude of the detection signal exceeds a predetermined normal amplitude within a predetermined time, and the value being physically equivalent to the rate.
    Type: Application
    Filed: June 20, 2019
    Publication date: January 30, 2020
    Inventors: Ryohei MATSUI, Nobuyuki SUGII, Tetsufumi KAWAMURA
  • Patent number: 10410826
    Abstract: The invention is directed to a technique for reducing the time from the start of fabrication of a prototype structure to the completion of fabrication of a real structure. A device processing method includes steps of: fabricating a first structure using an ion beam under a first condition in a first region on a substrate; measuring a size of the first structure which is fabricated; comparing the measurement result with design data; determining a second condition from the comparison result; and fabricating a second structure using the ion beam under the second condition in a second region on the substrate.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: September 10, 2019
    Assignee: HITACHI, LTD.
    Inventors: Tetsufumi Kawamura, Misuzu Sagawa, Kazuki Watanabe, Keiji Watanabe, Shuntaro Machida, Nobuyuki Sugii, Daisuke Ryuzaki
  • Patent number: 10336609
    Abstract: First, an ion beam is applied to a workpiece to form a tapered hole the side wall of which is inclined. Next, the application of the ion beam is stopped, and then a material gas is introduced from the gas source to the upper surface of the workpiece from an oblique direction to cause gas molecules to be adsorbed to the upper surface of the workpiece and to the upper portion of the side wall of the hole. Next, introduction of the material gas is stopped, and then the ion beam is applied again to the region of the workpiece where the hole is formed. As a result, at the upper portion of the side wall of the hole, film formation occurs using the gas molecules as the material adsorbed to the side wall of the hole, and, at the bottom portion of the hole, etching of the workpiece occurs.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 2, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Keiji Watanabe, Shuntaro Machida, Katsuya Miura, Aki Takei, Tetsufumi Kawamura, Nobuyuki Sugii, Daisuke Ryuzaki
  • Patent number: 10203688
    Abstract: A manufacturing device inputs design information including three-dimensional structure data, generates a manufacturing process flow, and displays the manufacturing process flow on a screen for a user to check, modify, and confirm the flow based on design information and setting information. A process method includes a first process method of a direct modeling method having an FIB method and a second process method of a semiconductor manufacturing process method which is a non-FIB method. The manufacturing device generates a plurality of manufacturing process flows by a combination of cases where each of the process methods is applied to each of the regions of the three-dimensional data. The manufacturing process flow includes a process device, the process method, a control parameter value, a process time, and a total process time for each of process steps. An output unit outputs a manufacturing process flow having, for example, the shortest total process time.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: February 12, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Masaharu Kinoshita, Nobuyuki Sugii, Tomonori Sekiguchi, Shuntaro Machida, Tetsufumi Kawamura
  • Publication number: 20190013179
    Abstract: The invention is directed to a technique for reducing the time from the start of fabrication of a prototype structure to the completion of fabrication of a real structure. A device processing method includes steps of: fabricating a first structure using an ion beam under a first condition in a first region on a substrate; measuring a size of the first structure which is fabricated; comparing the measurement result with design data; determining a second condition from the comparison result; and fabricating a second structure using the ion beam under the second condition in a second region on the substrate.
    Type: Application
    Filed: March 18, 2016
    Publication date: January 10, 2019
    Applicant: HITACHI, LTD.
    Inventors: Tetsufumi KAWAMURA, Misuzu SAGAWA, Kazuki WATANABE, Keiji WATANABE, Shuntaro MACHIDA, Nobuyuki SUGII, Daisuke RYUZAKI
  • Publication number: 20180273378
    Abstract: Provided is a technology that enables the shortening of the designing period. A device designing method includes a step of extracting a structure compatible with requested characteristics from a database in which each structure of a device is associated with characteristics and a step of outputting the extracted structure and a tuning parameter for adjusting the structure into ranges of the requested characteristics. In regard to each structure parameter determining the structure of the device, characteristics obtained by performing a simulation while exhaustively changing the structure parameter in a manufacturable range and the structure parameter used for the simulation are stored in the database while being associated with each other.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 27, 2018
    Inventors: Tetsufumi KAWAMURA, Kazuki WATANABE, Atsushi ISOBE, Yuudai KAMADA, Shuntaro MACHIDA, Nobuyuki SUGII, Daisuke RYUZAKI
  • Publication number: 20180267075
    Abstract: For the purpose of shortening the MEMS manufacturing TAT, the MEMS manufacturing method according to the present invention includes a step of extracting the first MEMS with first characteristic in a range approximate to the required characteristic from the plurality of MEMS preliminarily prepared on the main surface of the substrate, and a step of forming a second MEMS having the required characteristic by directly processing the first MEMS.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 20, 2018
    Inventors: Shuntaro MACHIDA, Nobuyuki SUGII, Keiji WATANABE, Daisuke RYUZAKI, Tetsufumi KAWAMURA, Kazuki WATANABE
  • Patent number: 10068932
    Abstract: A display device for improving an aperture ratio of the pixel is provided. In the display device, a transparent oxide layer, an insulating film, and a conductive layer are sequentially stacked on a pixel region on a substrate, the conductive layer has a gate electrode of a thin film transistor connected to a gate signal line, and a region of the transparent oxide layer other than at least a channel region portion directly below the gate electrode is converted into an electrically conductive region, and a source signal line, a source region portion of the thin film transistor connected to the source signal line, a pixel electrode, and a drain region portion of the thin film transistor connected to the pixel electrode are formed from the conductive region.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: September 4, 2018
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Tetsufumi Kawamura, Takeshi Sato, Mutsuko Hatano, Yoshiaki Toyota
  • Patent number: 10002801
    Abstract: The device manufacturing method includes a length measuring step (S5) of, on the basis of an observation target image of an SEM image taken from a direction having a predetermined angle from a direction perpendicular to a plane of a substrate, measuring the thickness of a target object, or the depth of etching, formed on the substrate. In addition, in the length measuring step, an etching angle made by a cross section of the etching and the direction perpendicular to the plane of the substrate is calculated from processing data of the target object, and the thickness of the target object or the depth of the etching is measured on the basis of the calculated etching angle.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 19, 2018
    Assignee: HITACHI, LTD.
    Inventors: Misuzu Sagawa, Tetsufumi Kawamura
  • Publication number: 20180137212
    Abstract: Provided is a device design support apparatus in which a data input-output portion receives an input of a first device provisional specification relating to a device from a customer, a database generating portion generates a second database based on a first database stored in a database storing portion and the first device provisional specification, and a device specification generating portion generates a second device provisional specification relating to the device based on the second database, presents the second device provisional specification to the customer by outputting the generated second device provisional specification through the data input-output portion, receives the input of a change content of the second device provisional specification from the customer, and generates a device fixed specification of the device based on the second device provisional specification and the change content.
    Type: Application
    Filed: November 8, 2017
    Publication date: May 17, 2018
    Applicant: HITACHI, LTD.
    Inventors: Yuhua ZHANG, Tetsufumi KAWAMURA, Atsushi ISOBE, Nobuyuki SUGII, Daisuke RYUZAKI
  • Publication number: 20180121589
    Abstract: The present invention provides a technique for determining the circuit configuration and device structure that meet required specifications in a short time. A device design support method includes: a step (S2) of receiving an input of specifications of a sensor, and extracting the circuit configuration and device specification range corresponding to the received specifications of the sensor, by referring to a circuit design database in which the circuit configuration configuring the sensor, the range of the specifications of the device configuring the sensor, and the specifications of the sensor are associated with each other; and a step (S3) of extracting the device structure corresponding to the extracted device specification range by referring to a device design database in which the specifications of the device and the structure of the device are associated with each other.
    Type: Application
    Filed: October 19, 2017
    Publication date: May 3, 2018
    Inventors: Tetsufumi KAWAMURA, Nobuyuki SUGII, Yuudai KAMADA, Yuhua ZHANG, Atsushi ISOBE, Ryohei MATSUI, Daisuke RYUZAKI
  • Publication number: 20180017958
    Abstract: A manufacturing device inputs design information including three-dimensional structure data, generates a manufacturing process flow, and displays the manufacturing process flow on a screen for a user to check, modify, and confirm the flow based on design information and setting information. A process method includes a first process method of a direct modeling method having an FIB method and a second process method of a semiconductor manufacturing process method which is a non-FIB method. The manufacturing device generates a plurality of manufacturing process flows by a combination of cases where each of the process methods is applied to each of the regions of the three-dimensional data. The manufacturing process flow includes a process device, the process method, a control parameter value, a process time, and a total process time for each of process steps. An output unit outputs a manufacturing process flow having, for example, the shortest total process time.
    Type: Application
    Filed: May 12, 2017
    Publication date: January 18, 2018
    Inventors: Masaharu KINOSHITA, Nobuyuki SUGII, Tomonori SEKIGUCHI, Shuntaro MACHIDA, Tetsufumi KAWAMURA
  • Publication number: 20180005906
    Abstract: The device manufacturing method includes a length measuring step (S5) of, on the basis of an observation target image of an SEM image taken from a direction having a predetermined angle from a direction perpendicular to a plane of a substrate, measuring the thickness of a target object, or the depth of etching, formed on the substrate. In addition, in the length measuring step, an etching angle made by a cross section of the etching and the direction perpendicular to the plane of the substrate is calculated from processing data of the target object, and the thickness of the target object or the depth of the etching is measured on the basis of the calculated etching angle.
    Type: Application
    Filed: May 17, 2017
    Publication date: January 4, 2018
    Inventors: Misuzu SAGAWA, Tetsufumi KAWAMURA
  • Publication number: 20170362082
    Abstract: First, an ion beam is applied to a workpiece to form a tapered hole the side wall of which is inclined. Next, the application of the ion beam is stopped, and then a material gas is introduced from the gas source to the upper surface of the workpiece from an oblique direction to cause gas molecules to be adsorbed to the upper surface of the workpiece and to the upper portion of the side wall of the hole. Next, introduction of the material gas is stopped, and then the ion beam is applied again to the region of the workpiece where the hole is formed. As a result, at the upper portion of the side wall of the hole, film formation occurs using the gas molecules as the material adsorbed to the side wall of the hole, and, at the bottom portion of the hole, etching of the workpiece occurs.
    Type: Application
    Filed: June 1, 2017
    Publication date: December 21, 2017
    Inventors: Keiji WATANABE, Shuntaro MACHIDA, Katsuya MIURA, Aki TAKEI, Tetsufumi KAWAMURA, Nobuyuki SUGII, Daisuke RYUZAKI
  • Patent number: 8912537
    Abstract: Disclosed is an oxide semiconductor layer (13) which forms a channel for a thin-film transistor and which includes at least In and oxygen and one or more types of elements from among Zn, Cd, Al, Ga, Si, Sn, Ce, and Ge. A high concentration region (13d) is disposed on one section of the oxide semiconductor layer (13), whereby said region has a maximum In concentration 30 at %; or higher than other regions on the oxide semiconductor layer (13). The film thickness of the oxide semiconductor layer (13) is 100 nm max., and the film thickness of the high concentration region (13d) is 20 nm max. or, preferably, 6 nm max. This enables a thin-film transistor with a sub-threshold slope of 100 mV/decade max., a high on-current, and a high field effect mobility to be achieved.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: December 16, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Hironori Wakana, Tetsufumi Kawamura, Hiroyuki Uchiyama, Kuniharu Fujii
  • Publication number: 20140248748
    Abstract: A display device for improving an aperture ratio of the pixel is provided. In the display device, a transparent oxide layer, an insulating film, and a conductive layer are sequentially stacked on a pixel region on a substrate, the conductive layer has a gate electrode of a thin film transistor connected to a gate signal line, and a region of the transparent oxide layer other than at least a channel region portion directly below the gate electrode is converted into an electrically conductive region, and a source signal line, a source region portion of the thin film transistor connected to the source signal line, a pixel electrode, and a drain region portion of the thin film transistor connected to the pixel electrode are formed from the conductive region.
    Type: Application
    Filed: May 15, 2014
    Publication date: September 4, 2014
    Applicants: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Tetsufumi KAWAMURA, Takeshi SATO, Mutsuko HATANO, Yoshiaki TOYOTA, I
  • Patent number: 8803150
    Abstract: Provided a display device including a thin film transistor. The thin film transistor includes a gate electrode, a gate insulating layer which covers the gate electrode, an oxide semiconductor film above the gate insulating layer, a source electrode and a drain electrode which are respectively provided in contact with a first region and a second region, which are provided in the upper surface of the oxide semiconductor film, and a channel protective film which is provided in contact with a third region between the first region and the second region. In plan view, a region of the oxide semiconductor film, which overlaps with the gate electrode, is smaller than the third region, and a portion of the oxide semiconductor film except for a portion which overlaps with the gate electrode has a resistance lower than the portion.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: August 12, 2014
    Assignee: Japan Display Inc.
    Inventors: Takeshi Noda, Tetsufumi Kawamura
  • Publication number: 20140106490
    Abstract: A display device for improving an aperture ratio of the pixel is provided. In the display device, a transparent oxide layer, an insulating film, and a conductive layer are sequentially stacked on a pixel region on a substrate, the conductive layer has a gate electrode of a thin film transistor connected to a gate signal line, and a region of the transparent oxide layer other than at least a channel region portion directly below the gate electrode is converted into an electrically conductive region, and a source signal line, a source region portion of the thin film transistor connected to the source signal line, a pixel electrode, and a drain region portion of the thin film transistor connected to the pixel electrode are formed from the conductive region.
    Type: Application
    Filed: December 13, 2013
    Publication date: April 17, 2014
    Applicants: Panasonic Liquid Crystal Display Co., Ltd., Japan Display Inc.
    Inventors: Tetsufumi KAWAMURA, Takeshi SATO, Mutsuko HATANO, Yoshiaki TOYOTA
  • Patent number: 8653517
    Abstract: In a TFT that adopts an oxide semiconductor as an active layer and has a resistance layer interposed between the active layer and one of a source and drain electrode, while Vth close to 0 V and a small off current are sustained, an on-current is increased. In a thin-film transistor including a gate electrode, a gate insulating film, a semiconductor layer, a source electrode, and a drain electrode, the semiconductor layer that links the source electrode and drain electrode is made of a metal oxide. The semiconductor layer includes three regions of first, second, and third regions. The first region is connected with the source electrode, the third region is connected with the drain electrode, and the second region is connected between the first region and third region. The resistivities of the three regions have the relationship of the first region>the second region>the third region.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: February 18, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Tetsufumi Kawamura, Hiroyuki Uchiyama, Hironori Wakana