Abstract: According to a certain embodiment, a test board on which a device under test and a test executable integrated circuit configured to execute a test of the device under test are mounted, includes a first input/output terminal, a second input/output terminal, and a contact unit. The first input/output terminal connects a first measuring apparatus capable of supplying electric power to the test board and controlling the test executable integrated circuit. The second input/output terminal connects a second measuring apparatus capable of measuring electrical characteristics of the test executable integrated circuit. The contact unit is mounted on the test board through the second input/output terminal, and capable of electrically connecting the second measuring apparatus.

Abstract: A memory test apparatus according to the present embodiment comprises a first storage medium temporarily retaining a test result of memory cells of a device under test in a plurality of divided portions based on data output from the device under test. A first processor reads the divided test result from the first storage medium to compress the test result. A second storage medium is provided to respectively correspond to a plurality of the devices under test and receives the compressed test result from the first processor and saves the compressed test result.

Abstract: A memory test apparatus according to the present embodiment comprises a first storage medium temporarily retaining a test result of memory cells of a device under test in a plurality of divided portions based on data output from the device under test. A first processor reads the divided test result from the first storage medium to compress the test result. A second storage medium is provided to respectively correspond to a plurality of the devices under test and receives the compressed test result from the first processor and saves the compressed test result.